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5b9fa9cbe6
Add support for RZ/G1H (R8A7742) SoC power areas to the R-Car SYSC driver. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> Link: https://lore.kernel.org/r/1587678050-23468-4-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
42 lines
1.4 KiB
C
42 lines
1.4 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Renesas RZ/G1H System Controller
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*
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* Copyright (C) 2020 Renesas Electronics Corp.
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*/
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#include <linux/kernel.h>
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#include <dt-bindings/power/r8a7742-sysc.h>
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#include "rcar-sysc.h"
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static const struct rcar_sysc_area r8a7742_areas[] __initconst = {
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{ "always-on", 0, 0, R8A7742_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
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{ "ca15-scu", 0x180, 0, R8A7742_PD_CA15_SCU, R8A7742_PD_ALWAYS_ON,
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PD_SCU },
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{ "ca15-cpu0", 0x40, 0, R8A7742_PD_CA15_CPU0, R8A7742_PD_CA15_SCU,
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PD_CPU_NOCR },
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{ "ca15-cpu1", 0x40, 1, R8A7742_PD_CA15_CPU1, R8A7742_PD_CA15_SCU,
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PD_CPU_NOCR },
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{ "ca15-cpu2", 0x40, 2, R8A7742_PD_CA15_CPU2, R8A7742_PD_CA15_SCU,
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PD_CPU_NOCR },
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{ "ca15-cpu3", 0x40, 3, R8A7742_PD_CA15_CPU3, R8A7742_PD_CA15_SCU,
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PD_CPU_NOCR },
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{ "ca7-scu", 0x100, 0, R8A7742_PD_CA7_SCU, R8A7742_PD_ALWAYS_ON,
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PD_SCU },
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{ "ca7-cpu0", 0x1c0, 0, R8A7742_PD_CA7_CPU0, R8A7742_PD_CA7_SCU,
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PD_CPU_NOCR },
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{ "ca7-cpu1", 0x1c0, 1, R8A7742_PD_CA7_CPU1, R8A7742_PD_CA7_SCU,
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PD_CPU_NOCR },
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{ "ca7-cpu2", 0x1c0, 2, R8A7742_PD_CA7_CPU2, R8A7742_PD_CA7_SCU,
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PD_CPU_NOCR },
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{ "ca7-cpu3", 0x1c0, 3, R8A7742_PD_CA7_CPU3, R8A7742_PD_CA7_SCU,
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PD_CPU_NOCR },
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{ "rgx", 0xc0, 0, R8A7742_PD_RGX, R8A7742_PD_ALWAYS_ON },
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};
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const struct rcar_sysc_info r8a7742_sysc_info __initconst = {
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.areas = r8a7742_areas,
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.num_areas = ARRAY_SIZE(r8a7742_areas),
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};
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