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![Yoshihiro Shimoda](/assets/img/avatar_default.png)
Add support for R-Car V4H (R8A779G0) SoC power areas and register access. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Link: https://lore.kernel.org/r/20220420084255.375700-10-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
379 lines
9.3 KiB
C
379 lines
9.3 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* R-Car Gen4 SYSC Power management support
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*
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* Copyright (C) 2021 Renesas Electronics Corp.
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*/
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#include <linux/bits.h>
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#include <linux/clk/renesas.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <linux/of_address.h>
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#include <linux/pm_domain.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include <linux/types.h>
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#include "rcar-gen4-sysc.h"
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/* SYSC Common */
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#define SYSCSR 0x000 /* SYSC Status Register */
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#define SYSCPONSR(x) (0x800 + ((x) * 0x4)) /* Power-ON Status Register 0 */
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#define SYSCPOFFSR(x) (0x808 + ((x) * 0x4)) /* Power-OFF Status Register */
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#define SYSCISCR(x) (0x810 + ((x) * 0x4)) /* Interrupt Status/Clear Register */
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#define SYSCIER(x) (0x820 + ((x) * 0x4)) /* Interrupt Enable Register */
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#define SYSCIMR(x) (0x830 + ((x) * 0x4)) /* Interrupt Mask Register */
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/* Power Domain Registers */
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#define PDRSR(n) (0x1000 + ((n) * 0x40))
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#define PDRONCR(n) (0x1004 + ((n) * 0x40))
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#define PDROFFCR(n) (0x1008 + ((n) * 0x40))
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#define PDRESR(n) (0x100C + ((n) * 0x40))
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/* PWRON/PWROFF */
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#define PWRON_PWROFF BIT(0) /* Power-ON/OFF request */
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/* PDRESR */
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#define PDRESR_ERR BIT(0)
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/* PDRSR */
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#define PDRSR_OFF BIT(0) /* Power-OFF state */
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#define PDRSR_ON BIT(4) /* Power-ON state */
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#define PDRSR_OFF_STATE BIT(8) /* Processing Power-OFF sequence */
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#define PDRSR_ON_STATE BIT(12) /* Processing Power-ON sequence */
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#define SYSCSR_BUSY GENMASK(1, 0) /* All bit sets is not busy */
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#define SYSCSR_TIMEOUT 10000
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#define SYSCSR_DELAY_US 10
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#define PDRESR_RETRIES 1000
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#define PDRESR_DELAY_US 10
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#define SYSCISR_TIMEOUT 10000
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#define SYSCISR_DELAY_US 10
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#define RCAR_GEN4_PD_ALWAYS_ON 64
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#define NUM_DOMAINS_EACH_REG BITS_PER_TYPE(u32)
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static void __iomem *rcar_gen4_sysc_base;
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static DEFINE_SPINLOCK(rcar_gen4_sysc_lock); /* SMP CPUs + I/O devices */
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static int rcar_gen4_sysc_pwr_on_off(u8 pdr, bool on)
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{
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unsigned int reg_offs;
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u32 val;
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int ret;
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if (on)
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reg_offs = PDRONCR(pdr);
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else
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reg_offs = PDROFFCR(pdr);
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/* Wait until SYSC is ready to accept a power request */
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ret = readl_poll_timeout_atomic(rcar_gen4_sysc_base + SYSCSR, val,
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(val & SYSCSR_BUSY) == SYSCSR_BUSY,
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SYSCSR_DELAY_US, SYSCSR_TIMEOUT);
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if (ret < 0)
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return -EAGAIN;
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/* Submit power shutoff or power resume request */
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iowrite32(PWRON_PWROFF, rcar_gen4_sysc_base + reg_offs);
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return 0;
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}
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static int clear_irq_flags(unsigned int reg_idx, unsigned int isr_mask)
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{
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u32 val;
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int ret;
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iowrite32(isr_mask, rcar_gen4_sysc_base + SYSCISCR(reg_idx));
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ret = readl_poll_timeout_atomic(rcar_gen4_sysc_base + SYSCISCR(reg_idx),
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val, !(val & isr_mask),
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SYSCISR_DELAY_US, SYSCISR_TIMEOUT);
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if (ret < 0) {
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pr_err("\n %s : Can not clear IRQ flags in SYSCISCR", __func__);
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return -EIO;
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}
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return 0;
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}
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static int rcar_gen4_sysc_power(u8 pdr, bool on)
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{
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unsigned int isr_mask;
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unsigned int reg_idx, bit_idx;
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unsigned int status;
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unsigned long flags;
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int ret = 0;
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u32 val;
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int k;
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spin_lock_irqsave(&rcar_gen4_sysc_lock, flags);
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reg_idx = pdr / NUM_DOMAINS_EACH_REG;
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bit_idx = pdr % NUM_DOMAINS_EACH_REG;
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isr_mask = BIT(bit_idx);
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/*
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* The interrupt source needs to be enabled, but masked, to prevent the
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* CPU from receiving it.
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*/
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iowrite32(ioread32(rcar_gen4_sysc_base + SYSCIER(reg_idx)) | isr_mask,
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rcar_gen4_sysc_base + SYSCIER(reg_idx));
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iowrite32(ioread32(rcar_gen4_sysc_base + SYSCIMR(reg_idx)) | isr_mask,
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rcar_gen4_sysc_base + SYSCIMR(reg_idx));
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ret = clear_irq_flags(reg_idx, isr_mask);
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if (ret)
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goto out;
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/* Submit power shutoff or resume request until it was accepted */
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for (k = 0; k < PDRESR_RETRIES; k++) {
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ret = rcar_gen4_sysc_pwr_on_off(pdr, on);
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if (ret)
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goto out;
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status = ioread32(rcar_gen4_sysc_base + PDRESR(pdr));
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if (!(status & PDRESR_ERR))
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break;
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udelay(PDRESR_DELAY_US);
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}
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if (k == PDRESR_RETRIES) {
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ret = -EIO;
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goto out;
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}
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/* Wait until the power shutoff or resume request has completed * */
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ret = readl_poll_timeout_atomic(rcar_gen4_sysc_base + SYSCISCR(reg_idx),
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val, (val & isr_mask),
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SYSCISR_DELAY_US, SYSCISR_TIMEOUT);
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if (ret < 0) {
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ret = -EIO;
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goto out;
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}
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/* Clear interrupt flags */
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ret = clear_irq_flags(reg_idx, isr_mask);
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if (ret)
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goto out;
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out:
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spin_unlock_irqrestore(&rcar_gen4_sysc_lock, flags);
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pr_debug("sysc power %s domain %d: %08x -> %d\n", on ? "on" : "off",
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pdr, ioread32(rcar_gen4_sysc_base + SYSCISCR(reg_idx)), ret);
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return ret;
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}
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static bool rcar_gen4_sysc_power_is_off(u8 pdr)
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{
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unsigned int st;
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st = ioread32(rcar_gen4_sysc_base + PDRSR(pdr));
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if (st & PDRSR_OFF)
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return true;
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return false;
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}
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struct rcar_gen4_sysc_pd {
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struct generic_pm_domain genpd;
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u8 pdr;
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unsigned int flags;
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char name[];
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};
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static inline struct rcar_gen4_sysc_pd *to_rcar_gen4_pd(struct generic_pm_domain *d)
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{
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return container_of(d, struct rcar_gen4_sysc_pd, genpd);
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}
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static int rcar_gen4_sysc_pd_power_off(struct generic_pm_domain *genpd)
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{
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struct rcar_gen4_sysc_pd *pd = to_rcar_gen4_pd(genpd);
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pr_debug("%s: %s\n", __func__, genpd->name);
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return rcar_gen4_sysc_power(pd->pdr, false);
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}
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static int rcar_gen4_sysc_pd_power_on(struct generic_pm_domain *genpd)
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{
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struct rcar_gen4_sysc_pd *pd = to_rcar_gen4_pd(genpd);
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pr_debug("%s: %s\n", __func__, genpd->name);
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return rcar_gen4_sysc_power(pd->pdr, true);
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}
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static int __init rcar_gen4_sysc_pd_setup(struct rcar_gen4_sysc_pd *pd)
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{
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struct generic_pm_domain *genpd = &pd->genpd;
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const char *name = pd->genpd.name;
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int error;
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if (pd->flags & PD_CPU) {
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/*
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* This domain contains a CPU core and therefore it should
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* only be turned off if the CPU is not in use.
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*/
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pr_debug("PM domain %s contains %s\n", name, "CPU");
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genpd->flags |= GENPD_FLAG_ALWAYS_ON;
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} else if (pd->flags & PD_SCU) {
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/*
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* This domain contains an SCU and cache-controller, and
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* therefore it should only be turned off if the CPU cores are
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* not in use.
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*/
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pr_debug("PM domain %s contains %s\n", name, "SCU");
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genpd->flags |= GENPD_FLAG_ALWAYS_ON;
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} else if (pd->flags & PD_NO_CR) {
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/*
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* This domain cannot be turned off.
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*/
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genpd->flags |= GENPD_FLAG_ALWAYS_ON;
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}
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if (!(pd->flags & (PD_CPU | PD_SCU))) {
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/* Enable Clock Domain for I/O devices */
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genpd->flags |= GENPD_FLAG_PM_CLK | GENPD_FLAG_ACTIVE_WAKEUP;
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genpd->attach_dev = cpg_mssr_attach_dev;
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genpd->detach_dev = cpg_mssr_detach_dev;
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}
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genpd->power_off = rcar_gen4_sysc_pd_power_off;
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genpd->power_on = rcar_gen4_sysc_pd_power_on;
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if (pd->flags & (PD_CPU | PD_NO_CR)) {
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/* Skip CPUs (handled by SMP code) and areas without control */
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pr_debug("%s: Not touching %s\n", __func__, genpd->name);
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goto finalize;
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}
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if (!rcar_gen4_sysc_power_is_off(pd->pdr)) {
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pr_debug("%s: %s is already powered\n", __func__, genpd->name);
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goto finalize;
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}
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rcar_gen4_sysc_power(pd->pdr, true);
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finalize:
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error = pm_genpd_init(genpd, &simple_qos_governor, false);
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if (error)
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pr_err("Failed to init PM domain %s: %d\n", name, error);
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return error;
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}
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static const struct of_device_id rcar_gen4_sysc_matches[] __initconst = {
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#ifdef CONFIG_SYSC_R8A779A0
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{ .compatible = "renesas,r8a779a0-sysc", .data = &r8a779a0_sysc_info },
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#endif
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#ifdef CONFIG_SYSC_R8A779F0
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{ .compatible = "renesas,r8a779f0-sysc", .data = &r8a779f0_sysc_info },
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#endif
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#ifdef CONFIG_SYSC_R8A779G0
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{ .compatible = "renesas,r8a779g0-sysc", .data = &r8a779g0_sysc_info },
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#endif
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{ /* sentinel */ }
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};
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struct rcar_gen4_pm_domains {
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struct genpd_onecell_data onecell_data;
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struct generic_pm_domain *domains[RCAR_GEN4_PD_ALWAYS_ON + 1];
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};
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static struct genpd_onecell_data *rcar_gen4_sysc_onecell_data;
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static int __init rcar_gen4_sysc_pd_init(void)
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{
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const struct rcar_gen4_sysc_info *info;
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const struct of_device_id *match;
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struct rcar_gen4_pm_domains *domains;
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struct device_node *np;
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void __iomem *base;
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unsigned int i;
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int error;
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np = of_find_matching_node_and_match(NULL, rcar_gen4_sysc_matches, &match);
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if (!np)
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return -ENODEV;
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info = match->data;
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base = of_iomap(np, 0);
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if (!base) {
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pr_warn("%pOF: Cannot map regs\n", np);
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error = -ENOMEM;
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goto out_put;
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}
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rcar_gen4_sysc_base = base;
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domains = kzalloc(sizeof(*domains), GFP_KERNEL);
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if (!domains) {
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error = -ENOMEM;
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goto out_put;
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}
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domains->onecell_data.domains = domains->domains;
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domains->onecell_data.num_domains = ARRAY_SIZE(domains->domains);
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rcar_gen4_sysc_onecell_data = &domains->onecell_data;
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for (i = 0; i < info->num_areas; i++) {
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const struct rcar_gen4_sysc_area *area = &info->areas[i];
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struct rcar_gen4_sysc_pd *pd;
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size_t n;
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if (!area->name) {
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/* Skip NULLified area */
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continue;
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}
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n = strlen(area->name) + 1;
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pd = kzalloc(sizeof(*pd) + n, GFP_KERNEL);
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if (!pd) {
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error = -ENOMEM;
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goto out_put;
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}
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memcpy(pd->name, area->name, n);
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pd->genpd.name = pd->name;
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pd->pdr = area->pdr;
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pd->flags = area->flags;
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error = rcar_gen4_sysc_pd_setup(pd);
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if (error)
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goto out_put;
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domains->domains[area->pdr] = &pd->genpd;
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if (area->parent < 0)
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continue;
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error = pm_genpd_add_subdomain(domains->domains[area->parent],
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&pd->genpd);
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if (error) {
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pr_warn("Failed to add PM subdomain %s to parent %u\n",
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area->name, area->parent);
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goto out_put;
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}
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}
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error = of_genpd_add_provider_onecell(np, &domains->onecell_data);
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out_put:
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of_node_put(np);
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return error;
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}
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early_initcall(rcar_gen4_sysc_pd_init);
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