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![Rob Herring](/assets/img/avatar_default.png)
It is preferred to use typed property access functions (i.e. of_property_read_<type> functions) rather than low-level of_get_property/of_find_property functions for reading properties. Convert reading boolean properties to of_property_read_bool(). Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Nishanth Menon <nm@ti.com> Link: https://lore.kernel.org/r/20230310144726.1545453-1-robh@kernel.org
811 lines
20 KiB
C
811 lines
20 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2014 Texas Instruments Incorporated
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* Authors: Santosh Shilimkar <santosh.shilimkar@ti.com>
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* Sandeep Nair <sandeep_n@ti.com>
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* Cyril Chemparathy <cyril@ti.com>
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*/
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#include <linux/io.h>
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#include <linux/sched.h>
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#include <linux/module.h>
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#include <linux/dma-direction.h>
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#include <linux/interrupt.h>
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#include <linux/pm_runtime.h>
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#include <linux/of_dma.h>
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#include <linux/of_address.h>
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#include <linux/platform_device.h>
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#include <linux/soc/ti/knav_dma.h>
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#include <linux/debugfs.h>
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#include <linux/seq_file.h>
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#define REG_MASK 0xffffffff
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#define DMA_LOOPBACK BIT(31)
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#define DMA_ENABLE BIT(31)
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#define DMA_TEARDOWN BIT(30)
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#define DMA_TX_FILT_PSWORDS BIT(29)
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#define DMA_TX_FILT_EINFO BIT(30)
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#define DMA_TX_PRIO_SHIFT 0
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#define DMA_RX_PRIO_SHIFT 16
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#define DMA_PRIO_MASK GENMASK(3, 0)
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#define DMA_PRIO_DEFAULT 0
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#define DMA_RX_TIMEOUT_DEFAULT 17500 /* cycles */
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#define DMA_RX_TIMEOUT_MASK GENMASK(16, 0)
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#define DMA_RX_TIMEOUT_SHIFT 0
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#define CHAN_HAS_EPIB BIT(30)
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#define CHAN_HAS_PSINFO BIT(29)
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#define CHAN_ERR_RETRY BIT(28)
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#define CHAN_PSINFO_AT_SOP BIT(25)
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#define CHAN_SOP_OFF_SHIFT 16
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#define CHAN_SOP_OFF_MASK GENMASK(9, 0)
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#define DESC_TYPE_SHIFT 26
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#define DESC_TYPE_MASK GENMASK(2, 0)
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/*
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* QMGR & QNUM together make up 14 bits with QMGR as the 2 MSb's in the logical
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* navigator cloud mapping scheme.
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* using the 14bit physical queue numbers directly maps into this scheme.
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*/
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#define CHAN_QNUM_MASK GENMASK(14, 0)
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#define DMA_MAX_QMS 4
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#define DMA_TIMEOUT 1 /* msecs */
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#define DMA_INVALID_ID 0xffff
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struct reg_global {
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u32 revision;
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u32 perf_control;
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u32 emulation_control;
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u32 priority_control;
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u32 qm_base_address[DMA_MAX_QMS];
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};
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struct reg_chan {
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u32 control;
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u32 mode;
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u32 __rsvd[6];
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};
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struct reg_tx_sched {
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u32 prio;
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};
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struct reg_rx_flow {
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u32 control;
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u32 tags;
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u32 tag_sel;
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u32 fdq_sel[2];
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u32 thresh[3];
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};
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struct knav_dma_pool_device {
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struct device *dev;
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struct list_head list;
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};
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struct knav_dma_device {
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bool loopback, enable_all;
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unsigned tx_priority, rx_priority, rx_timeout;
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unsigned logical_queue_managers;
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unsigned qm_base_address[DMA_MAX_QMS];
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struct reg_global __iomem *reg_global;
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struct reg_chan __iomem *reg_tx_chan;
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struct reg_rx_flow __iomem *reg_rx_flow;
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struct reg_chan __iomem *reg_rx_chan;
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struct reg_tx_sched __iomem *reg_tx_sched;
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unsigned max_rx_chan, max_tx_chan;
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unsigned max_rx_flow;
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char name[32];
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atomic_t ref_count;
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struct list_head list;
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struct list_head chan_list;
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spinlock_t lock;
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};
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struct knav_dma_chan {
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enum dma_transfer_direction direction;
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struct knav_dma_device *dma;
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atomic_t ref_count;
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/* registers */
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struct reg_chan __iomem *reg_chan;
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struct reg_tx_sched __iomem *reg_tx_sched;
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struct reg_rx_flow __iomem *reg_rx_flow;
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/* configuration stuff */
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unsigned channel, flow;
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struct knav_dma_cfg cfg;
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struct list_head list;
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spinlock_t lock;
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};
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#define chan_number(ch) ((ch->direction == DMA_MEM_TO_DEV) ? \
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ch->channel : ch->flow)
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static struct knav_dma_pool_device *kdev;
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static bool device_ready;
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bool knav_dma_device_ready(void)
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{
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return device_ready;
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}
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EXPORT_SYMBOL_GPL(knav_dma_device_ready);
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static bool check_config(struct knav_dma_chan *chan, struct knav_dma_cfg *cfg)
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{
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if (!memcmp(&chan->cfg, cfg, sizeof(*cfg)))
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return true;
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else
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return false;
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}
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static int chan_start(struct knav_dma_chan *chan,
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struct knav_dma_cfg *cfg)
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{
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u32 v = 0;
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spin_lock(&chan->lock);
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if ((chan->direction == DMA_MEM_TO_DEV) && chan->reg_chan) {
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if (cfg->u.tx.filt_pswords)
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v |= DMA_TX_FILT_PSWORDS;
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if (cfg->u.tx.filt_einfo)
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v |= DMA_TX_FILT_EINFO;
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writel_relaxed(v, &chan->reg_chan->mode);
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writel_relaxed(DMA_ENABLE, &chan->reg_chan->control);
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}
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if (chan->reg_tx_sched)
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writel_relaxed(cfg->u.tx.priority, &chan->reg_tx_sched->prio);
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if (chan->reg_rx_flow) {
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v = 0;
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if (cfg->u.rx.einfo_present)
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v |= CHAN_HAS_EPIB;
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if (cfg->u.rx.psinfo_present)
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v |= CHAN_HAS_PSINFO;
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if (cfg->u.rx.err_mode == DMA_RETRY)
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v |= CHAN_ERR_RETRY;
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v |= (cfg->u.rx.desc_type & DESC_TYPE_MASK) << DESC_TYPE_SHIFT;
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if (cfg->u.rx.psinfo_at_sop)
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v |= CHAN_PSINFO_AT_SOP;
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v |= (cfg->u.rx.sop_offset & CHAN_SOP_OFF_MASK)
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<< CHAN_SOP_OFF_SHIFT;
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v |= cfg->u.rx.dst_q & CHAN_QNUM_MASK;
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writel_relaxed(v, &chan->reg_rx_flow->control);
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writel_relaxed(0, &chan->reg_rx_flow->tags);
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writel_relaxed(0, &chan->reg_rx_flow->tag_sel);
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v = cfg->u.rx.fdq[0] << 16;
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v |= cfg->u.rx.fdq[1] & CHAN_QNUM_MASK;
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writel_relaxed(v, &chan->reg_rx_flow->fdq_sel[0]);
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v = cfg->u.rx.fdq[2] << 16;
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v |= cfg->u.rx.fdq[3] & CHAN_QNUM_MASK;
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writel_relaxed(v, &chan->reg_rx_flow->fdq_sel[1]);
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writel_relaxed(0, &chan->reg_rx_flow->thresh[0]);
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writel_relaxed(0, &chan->reg_rx_flow->thresh[1]);
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writel_relaxed(0, &chan->reg_rx_flow->thresh[2]);
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}
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/* Keep a copy of the cfg */
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memcpy(&chan->cfg, cfg, sizeof(*cfg));
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spin_unlock(&chan->lock);
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return 0;
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}
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static int chan_teardown(struct knav_dma_chan *chan)
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{
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unsigned long end, value;
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if (!chan->reg_chan)
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return 0;
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/* indicate teardown */
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writel_relaxed(DMA_TEARDOWN, &chan->reg_chan->control);
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/* wait for the dma to shut itself down */
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end = jiffies + msecs_to_jiffies(DMA_TIMEOUT);
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do {
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value = readl_relaxed(&chan->reg_chan->control);
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if ((value & DMA_ENABLE) == 0)
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break;
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} while (time_after(end, jiffies));
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if (readl_relaxed(&chan->reg_chan->control) & DMA_ENABLE) {
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dev_err(kdev->dev, "timeout waiting for teardown\n");
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return -ETIMEDOUT;
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}
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return 0;
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}
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static void chan_stop(struct knav_dma_chan *chan)
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{
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spin_lock(&chan->lock);
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if (chan->reg_rx_flow) {
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/* first detach fdqs, starve out the flow */
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writel_relaxed(0, &chan->reg_rx_flow->fdq_sel[0]);
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writel_relaxed(0, &chan->reg_rx_flow->fdq_sel[1]);
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writel_relaxed(0, &chan->reg_rx_flow->thresh[0]);
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writel_relaxed(0, &chan->reg_rx_flow->thresh[1]);
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writel_relaxed(0, &chan->reg_rx_flow->thresh[2]);
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}
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/* teardown the dma channel */
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chan_teardown(chan);
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/* then disconnect the completion side */
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if (chan->reg_rx_flow) {
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writel_relaxed(0, &chan->reg_rx_flow->control);
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writel_relaxed(0, &chan->reg_rx_flow->tags);
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writel_relaxed(0, &chan->reg_rx_flow->tag_sel);
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}
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memset(&chan->cfg, 0, sizeof(struct knav_dma_cfg));
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spin_unlock(&chan->lock);
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dev_dbg(kdev->dev, "channel stopped\n");
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}
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static void dma_hw_enable_all(struct knav_dma_device *dma)
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{
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int i;
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for (i = 0; i < dma->max_tx_chan; i++) {
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writel_relaxed(0, &dma->reg_tx_chan[i].mode);
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writel_relaxed(DMA_ENABLE, &dma->reg_tx_chan[i].control);
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}
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}
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static void knav_dma_hw_init(struct knav_dma_device *dma)
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{
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unsigned v;
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int i;
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spin_lock(&dma->lock);
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v = dma->loopback ? DMA_LOOPBACK : 0;
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writel_relaxed(v, &dma->reg_global->emulation_control);
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v = readl_relaxed(&dma->reg_global->perf_control);
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v |= ((dma->rx_timeout & DMA_RX_TIMEOUT_MASK) << DMA_RX_TIMEOUT_SHIFT);
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writel_relaxed(v, &dma->reg_global->perf_control);
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v = ((dma->tx_priority << DMA_TX_PRIO_SHIFT) |
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(dma->rx_priority << DMA_RX_PRIO_SHIFT));
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writel_relaxed(v, &dma->reg_global->priority_control);
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/* Always enable all Rx channels. Rx paths are managed using flows */
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for (i = 0; i < dma->max_rx_chan; i++)
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writel_relaxed(DMA_ENABLE, &dma->reg_rx_chan[i].control);
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for (i = 0; i < dma->logical_queue_managers; i++)
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writel_relaxed(dma->qm_base_address[i],
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&dma->reg_global->qm_base_address[i]);
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spin_unlock(&dma->lock);
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}
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static void knav_dma_hw_destroy(struct knav_dma_device *dma)
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{
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int i;
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unsigned v;
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spin_lock(&dma->lock);
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v = ~DMA_ENABLE & REG_MASK;
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for (i = 0; i < dma->max_rx_chan; i++)
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writel_relaxed(v, &dma->reg_rx_chan[i].control);
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for (i = 0; i < dma->max_tx_chan; i++)
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writel_relaxed(v, &dma->reg_tx_chan[i].control);
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spin_unlock(&dma->lock);
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}
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static void dma_debug_show_channels(struct seq_file *s,
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struct knav_dma_chan *chan)
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{
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int i;
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seq_printf(s, "\t%s %d:\t",
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((chan->direction == DMA_MEM_TO_DEV) ? "tx chan" : "rx flow"),
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chan_number(chan));
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if (chan->direction == DMA_MEM_TO_DEV) {
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seq_printf(s, "einfo - %d, pswords - %d, priority - %d\n",
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chan->cfg.u.tx.filt_einfo,
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chan->cfg.u.tx.filt_pswords,
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chan->cfg.u.tx.priority);
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} else {
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seq_printf(s, "einfo - %d, psinfo - %d, desc_type - %d\n",
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chan->cfg.u.rx.einfo_present,
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chan->cfg.u.rx.psinfo_present,
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chan->cfg.u.rx.desc_type);
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seq_printf(s, "\t\t\tdst_q: [%d], thresh: %d fdq: ",
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chan->cfg.u.rx.dst_q,
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chan->cfg.u.rx.thresh);
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for (i = 0; i < KNAV_DMA_FDQ_PER_CHAN; i++)
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seq_printf(s, "[%d]", chan->cfg.u.rx.fdq[i]);
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seq_printf(s, "\n");
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}
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}
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static void dma_debug_show_devices(struct seq_file *s,
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struct knav_dma_device *dma)
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{
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struct knav_dma_chan *chan;
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list_for_each_entry(chan, &dma->chan_list, list) {
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if (atomic_read(&chan->ref_count))
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dma_debug_show_channels(s, chan);
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}
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}
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static int knav_dma_debug_show(struct seq_file *s, void *v)
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{
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struct knav_dma_device *dma;
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list_for_each_entry(dma, &kdev->list, list) {
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if (atomic_read(&dma->ref_count)) {
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seq_printf(s, "%s : max_tx_chan: (%d), max_rx_flows: (%d)\n",
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dma->name, dma->max_tx_chan, dma->max_rx_flow);
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dma_debug_show_devices(s, dma);
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}
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}
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return 0;
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}
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DEFINE_SHOW_ATTRIBUTE(knav_dma_debug);
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static int of_channel_match_helper(struct device_node *np, const char *name,
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const char **dma_instance)
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{
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struct of_phandle_args args;
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struct device_node *dma_node;
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int index;
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dma_node = of_parse_phandle(np, "ti,navigator-dmas", 0);
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if (!dma_node)
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return -ENODEV;
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*dma_instance = dma_node->name;
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index = of_property_match_string(np, "ti,navigator-dma-names", name);
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if (index < 0) {
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dev_err(kdev->dev, "No 'ti,navigator-dma-names' property\n");
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return -ENODEV;
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}
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if (of_parse_phandle_with_fixed_args(np, "ti,navigator-dmas",
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1, index, &args)) {
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dev_err(kdev->dev, "Missing the phandle args name %s\n", name);
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return -ENODEV;
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}
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if (args.args[0] < 0) {
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dev_err(kdev->dev, "Missing args for %s\n", name);
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return -ENODEV;
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}
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return args.args[0];
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}
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/**
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* knav_dma_open_channel() - try to setup an exclusive slave channel
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* @dev: pointer to client device structure
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* @name: slave channel name
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* @config: dma configuration parameters
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*
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* Returns pointer to appropriate DMA channel on success or error.
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*/
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void *knav_dma_open_channel(struct device *dev, const char *name,
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struct knav_dma_cfg *config)
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{
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struct knav_dma_device *dma = NULL, *iter1;
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struct knav_dma_chan *chan = NULL, *iter2;
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int chan_num = -1;
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const char *instance;
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if (!kdev) {
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pr_err("keystone-navigator-dma driver not registered\n");
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return (void *)-EINVAL;
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}
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chan_num = of_channel_match_helper(dev->of_node, name, &instance);
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if (chan_num < 0) {
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dev_err(kdev->dev, "No DMA instance with name %s\n", name);
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return (void *)-EINVAL;
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}
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dev_dbg(kdev->dev, "initializing %s channel %d from DMA %s\n",
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config->direction == DMA_MEM_TO_DEV ? "transmit" :
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config->direction == DMA_DEV_TO_MEM ? "receive" :
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"unknown", chan_num, instance);
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if (config->direction != DMA_MEM_TO_DEV &&
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config->direction != DMA_DEV_TO_MEM) {
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dev_err(kdev->dev, "bad direction\n");
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return (void *)-EINVAL;
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}
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/* Look for correct dma instance */
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list_for_each_entry(iter1, &kdev->list, list) {
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if (!strcmp(iter1->name, instance)) {
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dma = iter1;
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break;
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}
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}
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if (!dma) {
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dev_err(kdev->dev, "No DMA instance with name %s\n", instance);
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return (void *)-EINVAL;
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}
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/* Look for correct dma channel from dma instance */
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list_for_each_entry(iter2, &dma->chan_list, list) {
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if (config->direction == DMA_MEM_TO_DEV) {
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if (iter2->channel == chan_num) {
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chan = iter2;
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break;
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}
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} else {
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if (iter2->flow == chan_num) {
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chan = iter2;
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break;
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}
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}
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}
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if (!chan) {
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dev_err(kdev->dev, "channel %d is not in DMA %s\n",
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chan_num, instance);
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return (void *)-EINVAL;
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}
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if (atomic_read(&chan->ref_count) >= 1) {
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if (!check_config(chan, config)) {
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dev_err(kdev->dev, "channel %d config miss-match\n",
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chan_num);
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return (void *)-EINVAL;
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}
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}
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|
|
if (atomic_inc_return(&chan->dma->ref_count) <= 1)
|
|
knav_dma_hw_init(chan->dma);
|
|
|
|
if (atomic_inc_return(&chan->ref_count) <= 1)
|
|
chan_start(chan, config);
|
|
|
|
dev_dbg(kdev->dev, "channel %d opened from DMA %s\n",
|
|
chan_num, instance);
|
|
|
|
return chan;
|
|
}
|
|
EXPORT_SYMBOL_GPL(knav_dma_open_channel);
|
|
|
|
/**
|
|
* knav_dma_close_channel() - Destroy a dma channel
|
|
*
|
|
* @channel: dma channel handle
|
|
*
|
|
*/
|
|
void knav_dma_close_channel(void *channel)
|
|
{
|
|
struct knav_dma_chan *chan = channel;
|
|
|
|
if (!kdev) {
|
|
pr_err("keystone-navigator-dma driver not registered\n");
|
|
return;
|
|
}
|
|
|
|
if (atomic_dec_return(&chan->ref_count) <= 0)
|
|
chan_stop(chan);
|
|
|
|
if (atomic_dec_return(&chan->dma->ref_count) <= 0)
|
|
knav_dma_hw_destroy(chan->dma);
|
|
|
|
dev_dbg(kdev->dev, "channel %d or flow %d closed from DMA %s\n",
|
|
chan->channel, chan->flow, chan->dma->name);
|
|
}
|
|
EXPORT_SYMBOL_GPL(knav_dma_close_channel);
|
|
|
|
static void __iomem *pktdma_get_regs(struct knav_dma_device *dma,
|
|
struct device_node *node,
|
|
unsigned index, resource_size_t *_size)
|
|
{
|
|
struct device *dev = kdev->dev;
|
|
struct resource res;
|
|
void __iomem *regs;
|
|
int ret;
|
|
|
|
ret = of_address_to_resource(node, index, &res);
|
|
if (ret) {
|
|
dev_err(dev, "Can't translate of node(%pOFn) address for index(%d)\n",
|
|
node, index);
|
|
return ERR_PTR(ret);
|
|
}
|
|
|
|
regs = devm_ioremap_resource(kdev->dev, &res);
|
|
if (IS_ERR(regs))
|
|
dev_err(dev, "Failed to map register base for index(%d) node(%pOFn)\n",
|
|
index, node);
|
|
if (_size)
|
|
*_size = resource_size(&res);
|
|
|
|
return regs;
|
|
}
|
|
|
|
static int pktdma_init_rx_chan(struct knav_dma_chan *chan, u32 flow)
|
|
{
|
|
struct knav_dma_device *dma = chan->dma;
|
|
|
|
chan->flow = flow;
|
|
chan->reg_rx_flow = dma->reg_rx_flow + flow;
|
|
chan->channel = DMA_INVALID_ID;
|
|
dev_dbg(kdev->dev, "rx flow(%d) (%p)\n", chan->flow, chan->reg_rx_flow);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int pktdma_init_tx_chan(struct knav_dma_chan *chan, u32 channel)
|
|
{
|
|
struct knav_dma_device *dma = chan->dma;
|
|
|
|
chan->channel = channel;
|
|
chan->reg_chan = dma->reg_tx_chan + channel;
|
|
chan->reg_tx_sched = dma->reg_tx_sched + channel;
|
|
chan->flow = DMA_INVALID_ID;
|
|
dev_dbg(kdev->dev, "tx channel(%d) (%p)\n", chan->channel, chan->reg_chan);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int pktdma_init_chan(struct knav_dma_device *dma,
|
|
enum dma_transfer_direction dir,
|
|
unsigned chan_num)
|
|
{
|
|
struct device *dev = kdev->dev;
|
|
struct knav_dma_chan *chan;
|
|
int ret = -EINVAL;
|
|
|
|
chan = devm_kzalloc(dev, sizeof(*chan), GFP_KERNEL);
|
|
if (!chan)
|
|
return -ENOMEM;
|
|
|
|
INIT_LIST_HEAD(&chan->list);
|
|
chan->dma = dma;
|
|
chan->direction = DMA_TRANS_NONE;
|
|
atomic_set(&chan->ref_count, 0);
|
|
spin_lock_init(&chan->lock);
|
|
|
|
if (dir == DMA_MEM_TO_DEV) {
|
|
chan->direction = dir;
|
|
ret = pktdma_init_tx_chan(chan, chan_num);
|
|
} else if (dir == DMA_DEV_TO_MEM) {
|
|
chan->direction = dir;
|
|
ret = pktdma_init_rx_chan(chan, chan_num);
|
|
} else {
|
|
dev_err(dev, "channel(%d) direction unknown\n", chan_num);
|
|
}
|
|
|
|
list_add_tail(&chan->list, &dma->chan_list);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int dma_init(struct device_node *cloud, struct device_node *dma_node)
|
|
{
|
|
unsigned max_tx_chan, max_rx_chan, max_rx_flow, max_tx_sched;
|
|
struct device_node *node = dma_node;
|
|
struct knav_dma_device *dma;
|
|
int ret, len, num_chan = 0;
|
|
resource_size_t size;
|
|
u32 timeout;
|
|
u32 i;
|
|
|
|
dma = devm_kzalloc(kdev->dev, sizeof(*dma), GFP_KERNEL);
|
|
if (!dma) {
|
|
dev_err(kdev->dev, "could not allocate driver mem\n");
|
|
return -ENOMEM;
|
|
}
|
|
INIT_LIST_HEAD(&dma->list);
|
|
INIT_LIST_HEAD(&dma->chan_list);
|
|
|
|
if (!of_find_property(cloud, "ti,navigator-cloud-address", &len)) {
|
|
dev_err(kdev->dev, "unspecified navigator cloud addresses\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
dma->logical_queue_managers = len / sizeof(u32);
|
|
if (dma->logical_queue_managers > DMA_MAX_QMS) {
|
|
dev_warn(kdev->dev, "too many queue mgrs(>%d) rest ignored\n",
|
|
dma->logical_queue_managers);
|
|
dma->logical_queue_managers = DMA_MAX_QMS;
|
|
}
|
|
|
|
ret = of_property_read_u32_array(cloud, "ti,navigator-cloud-address",
|
|
dma->qm_base_address,
|
|
dma->logical_queue_managers);
|
|
if (ret) {
|
|
dev_err(kdev->dev, "invalid navigator cloud addresses\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
dma->reg_global = pktdma_get_regs(dma, node, 0, &size);
|
|
if (IS_ERR(dma->reg_global))
|
|
return PTR_ERR(dma->reg_global);
|
|
if (size < sizeof(struct reg_global)) {
|
|
dev_err(kdev->dev, "bad size %pa for global regs\n", &size);
|
|
return -ENODEV;
|
|
}
|
|
|
|
dma->reg_tx_chan = pktdma_get_regs(dma, node, 1, &size);
|
|
if (IS_ERR(dma->reg_tx_chan))
|
|
return PTR_ERR(dma->reg_tx_chan);
|
|
|
|
max_tx_chan = size / sizeof(struct reg_chan);
|
|
dma->reg_rx_chan = pktdma_get_regs(dma, node, 2, &size);
|
|
if (IS_ERR(dma->reg_rx_chan))
|
|
return PTR_ERR(dma->reg_rx_chan);
|
|
|
|
max_rx_chan = size / sizeof(struct reg_chan);
|
|
dma->reg_tx_sched = pktdma_get_regs(dma, node, 3, &size);
|
|
if (IS_ERR(dma->reg_tx_sched))
|
|
return PTR_ERR(dma->reg_tx_sched);
|
|
|
|
max_tx_sched = size / sizeof(struct reg_tx_sched);
|
|
dma->reg_rx_flow = pktdma_get_regs(dma, node, 4, &size);
|
|
if (IS_ERR(dma->reg_rx_flow))
|
|
return PTR_ERR(dma->reg_rx_flow);
|
|
|
|
max_rx_flow = size / sizeof(struct reg_rx_flow);
|
|
dma->rx_priority = DMA_PRIO_DEFAULT;
|
|
dma->tx_priority = DMA_PRIO_DEFAULT;
|
|
|
|
dma->enable_all = of_property_read_bool(node, "ti,enable-all");
|
|
dma->loopback = of_property_read_bool(node, "ti,loop-back");
|
|
|
|
ret = of_property_read_u32(node, "ti,rx-retry-timeout", &timeout);
|
|
if (ret < 0) {
|
|
dev_dbg(kdev->dev, "unspecified rx timeout using value %d\n",
|
|
DMA_RX_TIMEOUT_DEFAULT);
|
|
timeout = DMA_RX_TIMEOUT_DEFAULT;
|
|
}
|
|
|
|
dma->rx_timeout = timeout;
|
|
dma->max_rx_chan = max_rx_chan;
|
|
dma->max_rx_flow = max_rx_flow;
|
|
dma->max_tx_chan = min(max_tx_chan, max_tx_sched);
|
|
atomic_set(&dma->ref_count, 0);
|
|
strcpy(dma->name, node->name);
|
|
spin_lock_init(&dma->lock);
|
|
|
|
for (i = 0; i < dma->max_tx_chan; i++) {
|
|
if (pktdma_init_chan(dma, DMA_MEM_TO_DEV, i) >= 0)
|
|
num_chan++;
|
|
}
|
|
|
|
for (i = 0; i < dma->max_rx_flow; i++) {
|
|
if (pktdma_init_chan(dma, DMA_DEV_TO_MEM, i) >= 0)
|
|
num_chan++;
|
|
}
|
|
|
|
list_add_tail(&dma->list, &kdev->list);
|
|
|
|
/*
|
|
* For DSP software usecases or userpace transport software, setup all
|
|
* the DMA hardware resources.
|
|
*/
|
|
if (dma->enable_all) {
|
|
atomic_inc(&dma->ref_count);
|
|
knav_dma_hw_init(dma);
|
|
dma_hw_enable_all(dma);
|
|
}
|
|
|
|
dev_info(kdev->dev, "DMA %s registered %d logical channels, flows %d, tx chans: %d, rx chans: %d%s\n",
|
|
dma->name, num_chan, dma->max_rx_flow,
|
|
dma->max_tx_chan, dma->max_rx_chan,
|
|
dma->loopback ? ", loopback" : "");
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int knav_dma_probe(struct platform_device *pdev)
|
|
{
|
|
struct device *dev = &pdev->dev;
|
|
struct device_node *node = pdev->dev.of_node;
|
|
struct device_node *child;
|
|
int ret = 0;
|
|
|
|
if (!node) {
|
|
dev_err(&pdev->dev, "could not find device info\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
kdev = devm_kzalloc(dev,
|
|
sizeof(struct knav_dma_pool_device), GFP_KERNEL);
|
|
if (!kdev) {
|
|
dev_err(dev, "could not allocate driver mem\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
kdev->dev = dev;
|
|
INIT_LIST_HEAD(&kdev->list);
|
|
|
|
pm_runtime_enable(kdev->dev);
|
|
ret = pm_runtime_resume_and_get(kdev->dev);
|
|
if (ret < 0) {
|
|
dev_err(kdev->dev, "unable to enable pktdma, err %d\n", ret);
|
|
goto err_pm_disable;
|
|
}
|
|
|
|
/* Initialise all packet dmas */
|
|
for_each_child_of_node(node, child) {
|
|
ret = dma_init(node, child);
|
|
if (ret) {
|
|
of_node_put(child);
|
|
dev_err(&pdev->dev, "init failed with %d\n", ret);
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (list_empty(&kdev->list)) {
|
|
dev_err(dev, "no valid dma instance\n");
|
|
ret = -ENODEV;
|
|
goto err_put_sync;
|
|
}
|
|
|
|
debugfs_create_file("knav_dma", S_IFREG | S_IRUGO, NULL, NULL,
|
|
&knav_dma_debug_fops);
|
|
|
|
device_ready = true;
|
|
return ret;
|
|
|
|
err_put_sync:
|
|
pm_runtime_put_sync(kdev->dev);
|
|
err_pm_disable:
|
|
pm_runtime_disable(kdev->dev);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int knav_dma_remove(struct platform_device *pdev)
|
|
{
|
|
struct knav_dma_device *dma;
|
|
|
|
list_for_each_entry(dma, &kdev->list, list) {
|
|
if (atomic_dec_return(&dma->ref_count) == 0)
|
|
knav_dma_hw_destroy(dma);
|
|
}
|
|
|
|
pm_runtime_put_sync(&pdev->dev);
|
|
pm_runtime_disable(&pdev->dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct of_device_id of_match[] = {
|
|
{ .compatible = "ti,keystone-navigator-dma", },
|
|
{},
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(of, of_match);
|
|
|
|
static struct platform_driver knav_dma_driver = {
|
|
.probe = knav_dma_probe,
|
|
.remove = knav_dma_remove,
|
|
.driver = {
|
|
.name = "keystone-navigator-dma",
|
|
.of_match_table = of_match,
|
|
},
|
|
};
|
|
module_platform_driver(knav_dma_driver);
|
|
|
|
MODULE_LICENSE("GPL v2");
|
|
MODULE_DESCRIPTION("TI Keystone Navigator Packet DMA driver");
|
|
MODULE_AUTHOR("Sandeep Nair <sandeep_n@ti.com>");
|
|
MODULE_AUTHOR("Santosh Shilimkar <santosh.shilimkar@ti.com>");
|