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Arm SPEv1.3 adds new load/store operation subclasses for Memory Tagging Extension (MTE) and memory operations (MOPS). The memory operations are memcpy and memset. Add support for decoding these new subclasses in the raw decoding. Reviewed-by: Leo Yan <leo.yan@linaro.org Signed-off-by: Rob Herring <robh@kernel.org> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Ian Rogers <irogers@google.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: Jiri Olsa <jolsa@kernel.org> Cc: Leo Yan <leo.yan@linaro.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Link: https://lore.kernel.org/r/20230327162057.4057188-1-robh@kernel.org Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
159 lines
4.7 KiB
C
159 lines
4.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Arm Statistical Profiling Extensions (SPE) support
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* Copyright (c) 2017-2018, Arm Ltd.
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*/
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#ifndef INCLUDE__ARM_SPE_PKT_DECODER_H__
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#define INCLUDE__ARM_SPE_PKT_DECODER_H__
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#include <stddef.h>
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#include <stdint.h>
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#define ARM_SPE_PKT_DESC_MAX 256
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#define ARM_SPE_NEED_MORE_BYTES -1
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#define ARM_SPE_BAD_PACKET -2
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#define ARM_SPE_PKT_MAX_SZ 16
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enum arm_spe_pkt_type {
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ARM_SPE_BAD,
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ARM_SPE_PAD,
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ARM_SPE_END,
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ARM_SPE_TIMESTAMP,
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ARM_SPE_ADDRESS,
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ARM_SPE_COUNTER,
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ARM_SPE_CONTEXT,
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ARM_SPE_OP_TYPE,
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ARM_SPE_EVENTS,
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ARM_SPE_DATA_SOURCE,
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};
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struct arm_spe_pkt {
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enum arm_spe_pkt_type type;
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unsigned char index;
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uint64_t payload;
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};
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/* Short header (HEADER0) and extended header (HEADER1) */
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#define SPE_HEADER0_PAD 0x0
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#define SPE_HEADER0_END 0x1
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#define SPE_HEADER0_TIMESTAMP 0x71
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/* Mask for event & data source */
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#define SPE_HEADER0_MASK1 (GENMASK_ULL(7, 6) | GENMASK_ULL(3, 0))
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#define SPE_HEADER0_EVENTS 0x42
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#define SPE_HEADER0_SOURCE 0x43
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/* Mask for context & operation */
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#define SPE_HEADER0_MASK2 GENMASK_ULL(7, 2)
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#define SPE_HEADER0_CONTEXT 0x64
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#define SPE_HEADER0_OP_TYPE 0x48
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/* Mask for extended format */
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#define SPE_HEADER0_EXTENDED 0x20
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/* Mask for address & counter */
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#define SPE_HEADER0_MASK3 GENMASK_ULL(7, 3)
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#define SPE_HEADER0_ADDRESS 0xb0
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#define SPE_HEADER0_COUNTER 0x98
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#define SPE_HEADER1_ALIGNMENT 0x0
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#define SPE_HDR_SHORT_INDEX(h) ((h) & GENMASK_ULL(2, 0))
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#define SPE_HDR_EXTENDED_INDEX(h0, h1) (((h0) & GENMASK_ULL(1, 0)) << 3 | \
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SPE_HDR_SHORT_INDEX(h1))
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/* Address packet header */
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#define SPE_ADDR_PKT_HDR_INDEX_INS 0x0
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#define SPE_ADDR_PKT_HDR_INDEX_BRANCH 0x1
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#define SPE_ADDR_PKT_HDR_INDEX_DATA_VIRT 0x2
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#define SPE_ADDR_PKT_HDR_INDEX_DATA_PHYS 0x3
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#define SPE_ADDR_PKT_HDR_INDEX_PREV_BRANCH 0x4
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/* Address packet payload */
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#define SPE_ADDR_PKT_ADDR_BYTE7_SHIFT 56
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#define SPE_ADDR_PKT_ADDR_GET_BYTES_0_6(v) ((v) & GENMASK_ULL(55, 0))
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#define SPE_ADDR_PKT_ADDR_GET_BYTE_6(v) (((v) & GENMASK_ULL(55, 48)) >> 48)
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#define SPE_ADDR_PKT_GET_NS(v) (((v) & BIT_ULL(63)) >> 63)
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#define SPE_ADDR_PKT_GET_EL(v) (((v) & GENMASK_ULL(62, 61)) >> 61)
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#define SPE_ADDR_PKT_GET_CH(v) (((v) & BIT_ULL(62)) >> 62)
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#define SPE_ADDR_PKT_GET_PAT(v) (((v) & GENMASK_ULL(59, 56)) >> 56)
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#define SPE_ADDR_PKT_EL0 0
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#define SPE_ADDR_PKT_EL1 1
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#define SPE_ADDR_PKT_EL2 2
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#define SPE_ADDR_PKT_EL3 3
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/* Context packet header */
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#define SPE_CTX_PKT_HDR_INDEX(h) ((h) & GENMASK_ULL(1, 0))
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/* Counter packet header */
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#define SPE_CNT_PKT_HDR_INDEX_TOTAL_LAT 0x0
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#define SPE_CNT_PKT_HDR_INDEX_ISSUE_LAT 0x1
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#define SPE_CNT_PKT_HDR_INDEX_TRANS_LAT 0x2
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/* Event packet payload */
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enum arm_spe_events {
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EV_EXCEPTION_GEN = 0,
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EV_RETIRED = 1,
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EV_L1D_ACCESS = 2,
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EV_L1D_REFILL = 3,
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EV_TLB_ACCESS = 4,
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EV_TLB_WALK = 5,
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EV_NOT_TAKEN = 6,
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EV_MISPRED = 7,
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EV_LLC_ACCESS = 8,
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EV_LLC_MISS = 9,
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EV_REMOTE_ACCESS = 10,
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EV_ALIGNMENT = 11,
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EV_PARTIAL_PREDICATE = 17,
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EV_EMPTY_PREDICATE = 18,
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};
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/* Operation packet header */
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#define SPE_OP_PKT_HDR_CLASS(h) ((h) & GENMASK_ULL(1, 0))
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#define SPE_OP_PKT_HDR_CLASS_OTHER 0x0
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#define SPE_OP_PKT_HDR_CLASS_LD_ST_ATOMIC 0x1
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#define SPE_OP_PKT_HDR_CLASS_BR_ERET 0x2
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#define SPE_OP_PKT_IS_OTHER_SVE_OP(v) (((v) & (BIT(7) | BIT(3) | BIT(0))) == 0x8)
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#define SPE_OP_PKT_COND BIT(0)
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#define SPE_OP_PKT_LDST_SUBCLASS_GET(v) ((v) & GENMASK_ULL(7, 1))
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#define SPE_OP_PKT_LDST_SUBCLASS_GP_REG 0x0
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#define SPE_OP_PKT_LDST_SUBCLASS_SIMD_FP 0x4
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#define SPE_OP_PKT_LDST_SUBCLASS_UNSPEC_REG 0x10
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#define SPE_OP_PKT_LDST_SUBCLASS_NV_SYSREG 0x30
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#define SPE_OP_PKT_LDST_SUBCLASS_MTE_TAG 0x14
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#define SPE_OP_PKT_LDST_SUBCLASS_MEMCPY 0x20
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#define SPE_OP_PKT_LDST_SUBCLASS_MEMSET 0x25
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#define SPE_OP_PKT_IS_LDST_ATOMIC(v) (((v) & (GENMASK_ULL(7, 5) | BIT(1))) == 0x2)
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#define SPE_OP_PKT_AR BIT(4)
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#define SPE_OP_PKT_EXCL BIT(3)
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#define SPE_OP_PKT_AT BIT(2)
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#define SPE_OP_PKT_ST BIT(0)
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#define SPE_OP_PKT_IS_LDST_SVE(v) (((v) & (BIT(3) | BIT(1))) == 0x8)
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#define SPE_OP_PKT_SVE_SG BIT(7)
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/*
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* SVE effective vector length (EVL) is stored in byte 0 bits [6:4];
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* the length is rounded up to a power of two and use 32 as one step,
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* so EVL calculation is:
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*
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* 32 * (2 ^ bits [6:4]) = 32 << (bits [6:4])
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*/
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#define SPE_OP_PKG_SVE_EVL(v) (32 << (((v) & GENMASK_ULL(6, 4)) >> 4))
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#define SPE_OP_PKT_SVE_PRED BIT(2)
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#define SPE_OP_PKT_SVE_FP BIT(1)
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#define SPE_OP_PKT_IS_INDIRECT_BRANCH(v) (((v) & GENMASK_ULL(7, 1)) == 0x2)
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const char *arm_spe_pkt_name(enum arm_spe_pkt_type);
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int arm_spe_get_packet(const unsigned char *buf, size_t len,
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struct arm_spe_pkt *packet);
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int arm_spe_pkt_desc(const struct arm_spe_pkt *packet, char *buf, size_t len);
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#endif
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