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![James Clark](/assets/img/avatar_default.png)
Currently we assume all trace belongs to the host machine so when the decoder should be looking at the guest kernel maps it can crash because it looks at the host ones instead. Avoid one scenario (guest kernel running at EL1) by assigning the default guest machine to this trace. For userspace trace it's still not possible to determine guest vs host, but the PIDs should help in this case. Committer notes: Fixed up conflict with: perf addr_location: Add init/exit/copy functions That was only on tmp.perf-tools-next. Reviewed-by: Leo Yan <leo.yan@linaro.org> Signed-off-by: James Clark <james.clark@arm.com> Cc: Adrian Hunter <adrian.hunter@intel.com> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Ian Rogers <irogers@google.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: Jiri Olsa <jolsa@kernel.org> Cc: John Garry <john.g.garry@oracle.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Mike Leach <mike.leach@linaro.org> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Suzuki Poulouse <suzuki.poulose@arm.com> Cc: Will Deacon <will@kernel.org> Cc: coresight@lists.linaro.org Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20230612111403.100613-5-james.clark@arm.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
277 lines
7.7 KiB
C
277 lines
7.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright(C) 2015 Linaro Limited. All rights reserved.
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* Author: Mathieu Poirier <mathieu.poirier@linaro.org>
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*/
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#ifndef INCLUDE__UTIL_PERF_CS_ETM_H__
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#define INCLUDE__UTIL_PERF_CS_ETM_H__
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#include "debug.h"
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#include "util/event.h"
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#include <linux/bits.h>
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struct perf_session;
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struct perf_pmu;
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/*
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* Versioning header in case things need to change in the future. That way
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* decoding of old snapshot is still possible.
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*/
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enum {
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/* Starting with 0x0 */
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CS_HEADER_VERSION,
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/* PMU->type (32 bit), total # of CPUs (32 bit) */
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CS_PMU_TYPE_CPUS,
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CS_ETM_SNAPSHOT,
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CS_HEADER_VERSION_MAX,
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};
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/*
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* Update the version for new format.
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*
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* Version 1: format adds a param count to the per cpu metadata.
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* This allows easy adding of new metadata parameters.
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* Requires that new params always added after current ones.
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* Also allows client reader to handle file versions that are different by
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* checking the number of params in the file vs the number expected.
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*
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* Version 2: Drivers will use PERF_RECORD_AUX_OUTPUT_HW_ID to output
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* CoreSight Trace ID. ...TRACEIDR metadata will be set to legacy values
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* but with addition flags.
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*/
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#define CS_HEADER_CURRENT_VERSION 2
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/* Beginning of header common to both ETMv3 and V4 */
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enum {
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CS_ETM_MAGIC,
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CS_ETM_CPU,
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/* Number of trace config params in following ETM specific block */
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CS_ETM_NR_TRC_PARAMS,
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CS_ETM_COMMON_BLK_MAX_V1,
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};
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/* ETMv3/PTM metadata */
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enum {
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/* Dynamic, configurable parameters */
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CS_ETM_ETMCR = CS_ETM_COMMON_BLK_MAX_V1,
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CS_ETM_ETMTRACEIDR,
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/* RO, taken from sysFS */
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CS_ETM_ETMCCER,
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CS_ETM_ETMIDR,
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CS_ETM_PRIV_MAX,
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};
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/* define fixed version 0 length - allow new format reader to read old files. */
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#define CS_ETM_NR_TRC_PARAMS_V0 (CS_ETM_ETMIDR - CS_ETM_ETMCR + 1)
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/* ETMv4 metadata */
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enum {
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/* Dynamic, configurable parameters */
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CS_ETMV4_TRCCONFIGR = CS_ETM_COMMON_BLK_MAX_V1,
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CS_ETMV4_TRCTRACEIDR,
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/* RO, taken from sysFS */
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CS_ETMV4_TRCIDR0,
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CS_ETMV4_TRCIDR1,
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CS_ETMV4_TRCIDR2,
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CS_ETMV4_TRCIDR8,
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CS_ETMV4_TRCAUTHSTATUS,
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CS_ETMV4_TS_SOURCE,
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CS_ETMV4_PRIV_MAX,
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};
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/* define fixed version 0 length - allow new format reader to read old files. */
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#define CS_ETMV4_NR_TRC_PARAMS_V0 (CS_ETMV4_TRCAUTHSTATUS - CS_ETMV4_TRCCONFIGR + 1)
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/*
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* ETE metadata is ETMv4 plus TRCDEVARCH register and doesn't support header V0 since it was
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* added in header V1
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*/
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enum {
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/* Dynamic, configurable parameters */
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CS_ETE_TRCCONFIGR = CS_ETM_COMMON_BLK_MAX_V1,
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CS_ETE_TRCTRACEIDR,
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/* RO, taken from sysFS */
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CS_ETE_TRCIDR0,
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CS_ETE_TRCIDR1,
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CS_ETE_TRCIDR2,
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CS_ETE_TRCIDR8,
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CS_ETE_TRCAUTHSTATUS,
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CS_ETE_TRCDEVARCH,
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CS_ETE_TS_SOURCE,
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CS_ETE_PRIV_MAX
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};
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/*
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* Check for valid CoreSight trace ID. If an invalid value is present in the metadata,
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* then IDs are present in the hardware ID packet in the data file.
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*/
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#define CS_IS_VALID_TRACE_ID(id) ((id > 0) && (id < 0x70))
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/*
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* ETMv3 exception encoding number:
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* See Embedded Trace Macrocell specification (ARM IHI 0014Q)
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* table 7-12 Encoding of Exception[3:0] for non-ARMv7-M processors.
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*/
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enum {
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CS_ETMV3_EXC_NONE = 0,
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CS_ETMV3_EXC_DEBUG_HALT = 1,
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CS_ETMV3_EXC_SMC = 2,
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CS_ETMV3_EXC_HYP = 3,
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CS_ETMV3_EXC_ASYNC_DATA_ABORT = 4,
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CS_ETMV3_EXC_JAZELLE_THUMBEE = 5,
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CS_ETMV3_EXC_PE_RESET = 8,
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CS_ETMV3_EXC_UNDEFINED_INSTR = 9,
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CS_ETMV3_EXC_SVC = 10,
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CS_ETMV3_EXC_PREFETCH_ABORT = 11,
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CS_ETMV3_EXC_DATA_FAULT = 12,
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CS_ETMV3_EXC_GENERIC = 13,
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CS_ETMV3_EXC_IRQ = 14,
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CS_ETMV3_EXC_FIQ = 15,
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};
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/*
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* ETMv4 exception encoding number:
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* See ARM Embedded Trace Macrocell Architecture Specification (ARM IHI 0064D)
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* table 6-12 Possible values for the TYPE field in an Exception instruction
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* trace packet, for ARMv7-A/R and ARMv8-A/R PEs.
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*/
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enum {
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CS_ETMV4_EXC_RESET = 0,
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CS_ETMV4_EXC_DEBUG_HALT = 1,
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CS_ETMV4_EXC_CALL = 2,
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CS_ETMV4_EXC_TRAP = 3,
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CS_ETMV4_EXC_SYSTEM_ERROR = 4,
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CS_ETMV4_EXC_INST_DEBUG = 6,
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CS_ETMV4_EXC_DATA_DEBUG = 7,
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CS_ETMV4_EXC_ALIGNMENT = 10,
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CS_ETMV4_EXC_INST_FAULT = 11,
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CS_ETMV4_EXC_DATA_FAULT = 12,
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CS_ETMV4_EXC_IRQ = 14,
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CS_ETMV4_EXC_FIQ = 15,
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CS_ETMV4_EXC_END = 31,
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};
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enum cs_etm_sample_type {
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CS_ETM_EMPTY,
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CS_ETM_RANGE,
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CS_ETM_DISCONTINUITY,
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CS_ETM_EXCEPTION,
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CS_ETM_EXCEPTION_RET,
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};
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enum cs_etm_isa {
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CS_ETM_ISA_UNKNOWN,
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CS_ETM_ISA_A64,
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CS_ETM_ISA_A32,
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CS_ETM_ISA_T32,
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};
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struct cs_etm_queue;
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struct cs_etm_packet {
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enum cs_etm_sample_type sample_type;
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enum cs_etm_isa isa;
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u64 start_addr;
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u64 end_addr;
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u32 instr_count;
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u32 last_instr_type;
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u32 last_instr_subtype;
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u32 flags;
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u32 exception_number;
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bool last_instr_cond;
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bool last_instr_taken_branch;
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u8 last_instr_size;
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u8 trace_chan_id;
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int cpu;
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};
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#define CS_ETM_PACKET_MAX_BUFFER 1024
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/*
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* When working with per-thread scenarios the process under trace can
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* be scheduled on any CPU and as such, more than one traceID may be
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* associated with the same process. Since a traceID of '0' is illegal
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* as per the CoreSight architecture, use that specific value to
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* identify the queue where all packets (with any traceID) are
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* aggregated.
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*/
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#define CS_ETM_PER_THREAD_TRACEID 0
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struct cs_etm_packet_queue {
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u32 packet_count;
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u32 head;
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u32 tail;
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u32 instr_count;
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u64 cs_timestamp; /* Timestamp from trace data, converted to ns if possible */
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u64 next_cs_timestamp;
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struct cs_etm_packet packet_buffer[CS_ETM_PACKET_MAX_BUFFER];
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};
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#define KiB(x) ((x) * 1024)
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#define MiB(x) ((x) * 1024 * 1024)
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#define CS_ETM_INVAL_ADDR 0xdeadbeefdeadbeefUL
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#define BMVAL(val, lsb, msb) ((val & GENMASK(msb, lsb)) >> lsb)
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#define CS_ETM_HEADER_SIZE (CS_HEADER_VERSION_MAX * sizeof(u64))
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#define __perf_cs_etmv3_magic 0x3030303030303030ULL
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#define __perf_cs_etmv4_magic 0x4040404040404040ULL
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#define __perf_cs_ete_magic 0x5050505050505050ULL
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#define CS_ETMV3_PRIV_SIZE (CS_ETM_PRIV_MAX * sizeof(u64))
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#define CS_ETMV4_PRIV_SIZE (CS_ETMV4_PRIV_MAX * sizeof(u64))
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#define CS_ETE_PRIV_SIZE (CS_ETE_PRIV_MAX * sizeof(u64))
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#define INFO_HEADER_SIZE (sizeof(((struct perf_record_auxtrace_info *)0)->type) + \
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sizeof(((struct perf_record_auxtrace_info *)0)->reserved__))
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/* CoreSight trace ID is currently the bottom 7 bits of the value */
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#define CORESIGHT_TRACE_ID_VAL_MASK GENMASK(6, 0)
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/*
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* perf record will set the legacy meta data values as unused initially.
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* This allows perf report to manage the decoders created when dynamic
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* allocation in operation.
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*/
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#define CORESIGHT_TRACE_ID_UNUSED_FLAG BIT(31)
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/* Value to set for unused trace ID values */
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#define CORESIGHT_TRACE_ID_UNUSED_VAL 0x7F
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int cs_etm__process_auxtrace_info(union perf_event *event,
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struct perf_session *session);
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struct perf_event_attr *cs_etm_get_default_config(struct perf_pmu *pmu);
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enum cs_etm_pid_fmt {
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CS_ETM_PIDFMT_NONE,
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CS_ETM_PIDFMT_CTXTID,
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CS_ETM_PIDFMT_CTXTID2
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};
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#ifdef HAVE_CSTRACE_SUPPORT
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#include <opencsd/ocsd_if_types.h>
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int cs_etm__get_cpu(u8 trace_chan_id, int *cpu);
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enum cs_etm_pid_fmt cs_etm__get_pid_fmt(struct cs_etm_queue *etmq);
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int cs_etm__etmq_set_tid_el(struct cs_etm_queue *etmq, pid_t tid,
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u8 trace_chan_id, ocsd_ex_level el);
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bool cs_etm__etmq_is_timeless(struct cs_etm_queue *etmq);
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void cs_etm__etmq_set_traceid_queue_timestamp(struct cs_etm_queue *etmq,
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u8 trace_chan_id);
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struct cs_etm_packet_queue
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*cs_etm__etmq_get_packet_queue(struct cs_etm_queue *etmq, u8 trace_chan_id);
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int cs_etm__process_auxtrace_info_full(union perf_event *event __maybe_unused,
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struct perf_session *session __maybe_unused);
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u64 cs_etm__convert_sample_time(struct cs_etm_queue *etmq, u64 cs_timestamp);
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#else
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static inline int
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cs_etm__process_auxtrace_info_full(union perf_event *event __maybe_unused,
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struct perf_session *session __maybe_unused)
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{
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pr_err("\nCS ETM Trace: OpenCSD is not linked in, please recompile with CORESIGHT=1\n");
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return -1;
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}
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#endif
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#endif
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