mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-22 00:40:03 +00:00
582 lines
14 KiB
C
582 lines
14 KiB
C
/*
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* TI QSPI driver
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*
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* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
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* Author: Sourav Poddar <sourav.poddar@ti.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GPLv2.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/device.h>
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#include <linux/delay.h>
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#include <linux/dma-mapping.h>
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#include <linux/dmaengine.h>
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#include <linux/omap-dma.h>
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#include <linux/platform_device.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/slab.h>
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#include <linux/pm_runtime.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/pinctrl/consumer.h>
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#include <linux/spi/spi.h>
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struct ti_qspi_regs {
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u32 clkctrl;
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};
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struct ti_qspi {
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struct completion transfer_complete;
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/* list synchronization */
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struct mutex list_lock;
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struct spi_master *master;
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void __iomem *base;
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void __iomem *ctrl_base;
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void __iomem *mmap_base;
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struct clk *fclk;
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struct device *dev;
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struct ti_qspi_regs ctx_reg;
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u32 spi_max_frequency;
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u32 cmd;
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u32 dc;
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bool ctrl_mod;
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};
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#define QSPI_PID (0x0)
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#define QSPI_SYSCONFIG (0x10)
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#define QSPI_INTR_STATUS_RAW_SET (0x20)
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#define QSPI_INTR_STATUS_ENABLED_CLEAR (0x24)
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#define QSPI_INTR_ENABLE_SET_REG (0x28)
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#define QSPI_INTR_ENABLE_CLEAR_REG (0x2c)
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#define QSPI_SPI_CLOCK_CNTRL_REG (0x40)
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#define QSPI_SPI_DC_REG (0x44)
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#define QSPI_SPI_CMD_REG (0x48)
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#define QSPI_SPI_STATUS_REG (0x4c)
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#define QSPI_SPI_DATA_REG (0x50)
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#define QSPI_SPI_SETUP0_REG (0x54)
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#define QSPI_SPI_SWITCH_REG (0x64)
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#define QSPI_SPI_SETUP1_REG (0x58)
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#define QSPI_SPI_SETUP2_REG (0x5c)
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#define QSPI_SPI_SETUP3_REG (0x60)
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#define QSPI_SPI_DATA_REG_1 (0x68)
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#define QSPI_SPI_DATA_REG_2 (0x6c)
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#define QSPI_SPI_DATA_REG_3 (0x70)
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#define QSPI_COMPLETION_TIMEOUT msecs_to_jiffies(2000)
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#define QSPI_FCLK 192000000
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/* Clock Control */
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#define QSPI_CLK_EN (1 << 31)
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#define QSPI_CLK_DIV_MAX 0xffff
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/* Command */
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#define QSPI_EN_CS(n) (n << 28)
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#define QSPI_WLEN(n) ((n - 1) << 19)
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#define QSPI_3_PIN (1 << 18)
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#define QSPI_RD_SNGL (1 << 16)
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#define QSPI_WR_SNGL (2 << 16)
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#define QSPI_RD_DUAL (3 << 16)
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#define QSPI_RD_QUAD (7 << 16)
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#define QSPI_INVAL (4 << 16)
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#define QSPI_WC_CMD_INT_EN (1 << 14)
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#define QSPI_FLEN(n) ((n - 1) << 0)
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/* STATUS REGISTER */
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#define WC 0x02
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/* INTERRUPT REGISTER */
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#define QSPI_WC_INT_EN (1 << 1)
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#define QSPI_WC_INT_DISABLE (1 << 1)
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/* Device Control */
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#define QSPI_DD(m, n) (m << (3 + n * 8))
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#define QSPI_CKPHA(n) (1 << (2 + n * 8))
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#define QSPI_CSPOL(n) (1 << (1 + n * 8))
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#define QSPI_CKPOL(n) (1 << (n * 8))
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#define QSPI_FRAME 4096
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#define QSPI_AUTOSUSPEND_TIMEOUT 2000
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static inline unsigned long ti_qspi_read(struct ti_qspi *qspi,
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unsigned long reg)
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{
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return readl(qspi->base + reg);
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}
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static inline void ti_qspi_write(struct ti_qspi *qspi,
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unsigned long val, unsigned long reg)
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{
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writel(val, qspi->base + reg);
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}
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static int ti_qspi_setup(struct spi_device *spi)
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{
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struct ti_qspi *qspi = spi_master_get_devdata(spi->master);
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struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg;
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int clk_div = 0, ret;
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u32 clk_ctrl_reg, clk_rate, clk_mask;
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if (spi->master->busy) {
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dev_dbg(qspi->dev, "master busy doing other trasnfers\n");
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return -EBUSY;
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}
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if (!qspi->spi_max_frequency) {
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dev_err(qspi->dev, "spi max frequency not defined\n");
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return -EINVAL;
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}
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clk_rate = clk_get_rate(qspi->fclk);
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clk_div = DIV_ROUND_UP(clk_rate, qspi->spi_max_frequency) - 1;
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if (clk_div < 0) {
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dev_dbg(qspi->dev, "clock divider < 0, using /1 divider\n");
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return -EINVAL;
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}
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if (clk_div > QSPI_CLK_DIV_MAX) {
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dev_dbg(qspi->dev, "clock divider >%d , using /%d divider\n",
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QSPI_CLK_DIV_MAX, QSPI_CLK_DIV_MAX + 1);
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return -EINVAL;
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}
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dev_dbg(qspi->dev, "hz: %d, clock divider %d\n",
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qspi->spi_max_frequency, clk_div);
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ret = pm_runtime_get_sync(qspi->dev);
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if (ret < 0) {
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dev_err(qspi->dev, "pm_runtime_get_sync() failed\n");
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return ret;
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}
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clk_ctrl_reg = ti_qspi_read(qspi, QSPI_SPI_CLOCK_CNTRL_REG);
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clk_ctrl_reg &= ~QSPI_CLK_EN;
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/* disable SCLK */
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ti_qspi_write(qspi, clk_ctrl_reg, QSPI_SPI_CLOCK_CNTRL_REG);
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/* enable SCLK */
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clk_mask = QSPI_CLK_EN | clk_div;
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ti_qspi_write(qspi, clk_mask, QSPI_SPI_CLOCK_CNTRL_REG);
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ctx_reg->clkctrl = clk_mask;
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pm_runtime_mark_last_busy(qspi->dev);
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ret = pm_runtime_put_autosuspend(qspi->dev);
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if (ret < 0) {
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dev_err(qspi->dev, "pm_runtime_put_autosuspend() failed\n");
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return ret;
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}
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return 0;
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}
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static void ti_qspi_restore_ctx(struct ti_qspi *qspi)
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{
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struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg;
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ti_qspi_write(qspi, ctx_reg->clkctrl, QSPI_SPI_CLOCK_CNTRL_REG);
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}
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static int qspi_write_msg(struct ti_qspi *qspi, struct spi_transfer *t)
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{
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int wlen, count, ret;
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unsigned int cmd;
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const u8 *txbuf;
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txbuf = t->tx_buf;
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cmd = qspi->cmd | QSPI_WR_SNGL;
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count = t->len;
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wlen = t->bits_per_word >> 3; /* in bytes */
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while (count) {
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switch (wlen) {
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case 1:
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dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %02x\n",
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cmd, qspi->dc, *txbuf);
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writeb(*txbuf, qspi->base + QSPI_SPI_DATA_REG);
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break;
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case 2:
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dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %04x\n",
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cmd, qspi->dc, *txbuf);
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writew(*((u16 *)txbuf), qspi->base + QSPI_SPI_DATA_REG);
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break;
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case 4:
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dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %08x\n",
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cmd, qspi->dc, *txbuf);
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writel(*((u32 *)txbuf), qspi->base + QSPI_SPI_DATA_REG);
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break;
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}
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ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
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ret = wait_for_completion_timeout(&qspi->transfer_complete,
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QSPI_COMPLETION_TIMEOUT);
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if (ret == 0) {
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dev_err(qspi->dev, "write timed out\n");
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return -ETIMEDOUT;
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}
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txbuf += wlen;
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count -= wlen;
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}
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return 0;
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}
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static int qspi_read_msg(struct ti_qspi *qspi, struct spi_transfer *t)
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{
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int wlen, count, ret;
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unsigned int cmd;
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u8 *rxbuf;
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rxbuf = t->rx_buf;
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cmd = qspi->cmd;
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switch (t->rx_nbits) {
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case SPI_NBITS_DUAL:
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cmd |= QSPI_RD_DUAL;
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break;
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case SPI_NBITS_QUAD:
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cmd |= QSPI_RD_QUAD;
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break;
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default:
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cmd |= QSPI_RD_SNGL;
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break;
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}
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count = t->len;
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wlen = t->bits_per_word >> 3; /* in bytes */
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while (count) {
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dev_dbg(qspi->dev, "rx cmd %08x dc %08x\n", cmd, qspi->dc);
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ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG);
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ret = wait_for_completion_timeout(&qspi->transfer_complete,
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QSPI_COMPLETION_TIMEOUT);
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if (ret == 0) {
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dev_err(qspi->dev, "read timed out\n");
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return -ETIMEDOUT;
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}
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switch (wlen) {
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case 1:
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*rxbuf = readb(qspi->base + QSPI_SPI_DATA_REG);
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break;
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case 2:
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*((u16 *)rxbuf) = readw(qspi->base + QSPI_SPI_DATA_REG);
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break;
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case 4:
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*((u32 *)rxbuf) = readl(qspi->base + QSPI_SPI_DATA_REG);
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break;
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}
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rxbuf += wlen;
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count -= wlen;
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}
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return 0;
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}
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static int qspi_transfer_msg(struct ti_qspi *qspi, struct spi_transfer *t)
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{
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int ret;
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if (t->tx_buf) {
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ret = qspi_write_msg(qspi, t);
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if (ret) {
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dev_dbg(qspi->dev, "Error while writing\n");
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return ret;
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}
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}
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if (t->rx_buf) {
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ret = qspi_read_msg(qspi, t);
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if (ret) {
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dev_dbg(qspi->dev, "Error while reading\n");
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return ret;
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}
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}
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return 0;
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}
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static int ti_qspi_start_transfer_one(struct spi_master *master,
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struct spi_message *m)
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{
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struct ti_qspi *qspi = spi_master_get_devdata(master);
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struct spi_device *spi = m->spi;
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struct spi_transfer *t;
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int status = 0, ret;
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int frame_length;
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/* setup device control reg */
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qspi->dc = 0;
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if (spi->mode & SPI_CPHA)
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qspi->dc |= QSPI_CKPHA(spi->chip_select);
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if (spi->mode & SPI_CPOL)
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qspi->dc |= QSPI_CKPOL(spi->chip_select);
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if (spi->mode & SPI_CS_HIGH)
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qspi->dc |= QSPI_CSPOL(spi->chip_select);
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frame_length = (m->frame_length << 3) / spi->bits_per_word;
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frame_length = clamp(frame_length, 0, QSPI_FRAME);
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/* setup command reg */
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qspi->cmd = 0;
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qspi->cmd |= QSPI_EN_CS(spi->chip_select);
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qspi->cmd |= QSPI_FLEN(frame_length);
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qspi->cmd |= QSPI_WC_CMD_INT_EN;
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ti_qspi_write(qspi, QSPI_WC_INT_EN, QSPI_INTR_ENABLE_SET_REG);
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ti_qspi_write(qspi, qspi->dc, QSPI_SPI_DC_REG);
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mutex_lock(&qspi->list_lock);
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list_for_each_entry(t, &m->transfers, transfer_list) {
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qspi->cmd |= QSPI_WLEN(t->bits_per_word);
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ret = qspi_transfer_msg(qspi, t);
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if (ret) {
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dev_dbg(qspi->dev, "transfer message failed\n");
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mutex_unlock(&qspi->list_lock);
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return -EINVAL;
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}
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m->actual_length += t->len;
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}
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mutex_unlock(&qspi->list_lock);
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m->status = status;
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spi_finalize_current_message(master);
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ti_qspi_write(qspi, qspi->cmd | QSPI_INVAL, QSPI_SPI_CMD_REG);
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return status;
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}
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static irqreturn_t ti_qspi_isr(int irq, void *dev_id)
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{
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struct ti_qspi *qspi = dev_id;
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u16 int_stat;
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u32 stat;
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irqreturn_t ret = IRQ_HANDLED;
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int_stat = ti_qspi_read(qspi, QSPI_INTR_STATUS_ENABLED_CLEAR);
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stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG);
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if (!int_stat) {
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dev_dbg(qspi->dev, "No IRQ triggered\n");
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ret = IRQ_NONE;
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goto out;
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}
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ti_qspi_write(qspi, QSPI_WC_INT_DISABLE,
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QSPI_INTR_STATUS_ENABLED_CLEAR);
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if (stat & WC)
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complete(&qspi->transfer_complete);
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out:
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return ret;
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}
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static int ti_qspi_runtime_resume(struct device *dev)
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{
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struct ti_qspi *qspi;
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qspi = dev_get_drvdata(dev);
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ti_qspi_restore_ctx(qspi);
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return 0;
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}
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static const struct of_device_id ti_qspi_match[] = {
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{.compatible = "ti,dra7xxx-qspi" },
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{.compatible = "ti,am4372-qspi" },
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{},
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};
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MODULE_DEVICE_TABLE(of, ti_qspi_match);
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|
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static int ti_qspi_probe(struct platform_device *pdev)
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{
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struct ti_qspi *qspi;
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struct spi_master *master;
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struct resource *r, *res_ctrl, *res_mmap;
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struct device_node *np = pdev->dev.of_node;
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u32 max_freq;
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int ret = 0, num_cs, irq;
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master = spi_alloc_master(&pdev->dev, sizeof(*qspi));
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if (!master)
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return -ENOMEM;
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master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD;
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|
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master->bus_num = -1;
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master->flags = SPI_MASTER_HALF_DUPLEX;
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master->setup = ti_qspi_setup;
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master->auto_runtime_pm = true;
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master->transfer_one_message = ti_qspi_start_transfer_one;
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master->dev.of_node = pdev->dev.of_node;
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master->bits_per_word_mask = BIT(32 - 1) | BIT(16 - 1) | BIT(8 - 1);
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if (!of_property_read_u32(np, "num-cs", &num_cs))
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master->num_chipselect = num_cs;
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qspi = spi_master_get_devdata(master);
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qspi->master = master;
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qspi->dev = &pdev->dev;
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platform_set_drvdata(pdev, qspi);
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r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_base");
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if (r == NULL) {
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r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (r == NULL) {
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dev_err(&pdev->dev, "missing platform data\n");
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return -ENODEV;
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}
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}
|
|
|
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res_mmap = platform_get_resource_byname(pdev,
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IORESOURCE_MEM, "qspi_mmap");
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if (res_mmap == NULL) {
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res_mmap = platform_get_resource(pdev, IORESOURCE_MEM, 1);
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if (res_mmap == NULL) {
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dev_err(&pdev->dev,
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"memory mapped resource not required\n");
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return -ENODEV;
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}
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}
|
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|
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res_ctrl = platform_get_resource_byname(pdev,
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IORESOURCE_MEM, "qspi_ctrlmod");
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if (res_ctrl == NULL) {
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res_ctrl = platform_get_resource(pdev, IORESOURCE_MEM, 2);
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if (res_ctrl == NULL) {
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dev_dbg(&pdev->dev,
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"control module resources not required\n");
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}
|
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}
|
|
|
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irq = platform_get_irq(pdev, 0);
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if (irq < 0) {
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dev_err(&pdev->dev, "no irq resource?\n");
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return irq;
|
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}
|
|
|
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mutex_init(&qspi->list_lock);
|
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|
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qspi->base = devm_ioremap_resource(&pdev->dev, r);
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if (IS_ERR(qspi->base)) {
|
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ret = PTR_ERR(qspi->base);
|
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goto free_master;
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}
|
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|
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if (res_ctrl) {
|
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qspi->ctrl_mod = true;
|
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qspi->ctrl_base = devm_ioremap_resource(&pdev->dev, res_ctrl);
|
|
if (IS_ERR(qspi->ctrl_base)) {
|
|
ret = PTR_ERR(qspi->ctrl_base);
|
|
goto free_master;
|
|
}
|
|
}
|
|
|
|
if (res_mmap) {
|
|
qspi->mmap_base = devm_ioremap_resource(&pdev->dev, res_mmap);
|
|
if (IS_ERR(qspi->mmap_base)) {
|
|
ret = PTR_ERR(qspi->mmap_base);
|
|
goto free_master;
|
|
}
|
|
}
|
|
|
|
ret = devm_request_irq(&pdev->dev, irq, ti_qspi_isr, 0,
|
|
dev_name(&pdev->dev), qspi);
|
|
if (ret < 0) {
|
|
dev_err(&pdev->dev, "Failed to register ISR for IRQ %d\n",
|
|
irq);
|
|
goto free_master;
|
|
}
|
|
|
|
qspi->fclk = devm_clk_get(&pdev->dev, "fck");
|
|
if (IS_ERR(qspi->fclk)) {
|
|
ret = PTR_ERR(qspi->fclk);
|
|
dev_err(&pdev->dev, "could not get clk: %d\n", ret);
|
|
}
|
|
|
|
init_completion(&qspi->transfer_complete);
|
|
|
|
pm_runtime_use_autosuspend(&pdev->dev);
|
|
pm_runtime_set_autosuspend_delay(&pdev->dev, QSPI_AUTOSUSPEND_TIMEOUT);
|
|
pm_runtime_enable(&pdev->dev);
|
|
|
|
if (!of_property_read_u32(np, "spi-max-frequency", &max_freq))
|
|
qspi->spi_max_frequency = max_freq;
|
|
|
|
ret = devm_spi_register_master(&pdev->dev, master);
|
|
if (ret)
|
|
goto free_master;
|
|
|
|
return 0;
|
|
|
|
free_master:
|
|
spi_master_put(master);
|
|
return ret;
|
|
}
|
|
|
|
static int ti_qspi_remove(struct platform_device *pdev)
|
|
{
|
|
struct ti_qspi *qspi = platform_get_drvdata(pdev);
|
|
int ret;
|
|
|
|
ret = pm_runtime_get_sync(qspi->dev);
|
|
if (ret < 0) {
|
|
dev_err(qspi->dev, "pm_runtime_get_sync() failed\n");
|
|
return ret;
|
|
}
|
|
|
|
ti_qspi_write(qspi, QSPI_WC_INT_DISABLE, QSPI_INTR_ENABLE_CLEAR_REG);
|
|
|
|
pm_runtime_put(qspi->dev);
|
|
pm_runtime_disable(&pdev->dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct dev_pm_ops ti_qspi_pm_ops = {
|
|
.runtime_resume = ti_qspi_runtime_resume,
|
|
};
|
|
|
|
static struct platform_driver ti_qspi_driver = {
|
|
.probe = ti_qspi_probe,
|
|
.remove = ti_qspi_remove,
|
|
.driver = {
|
|
.name = "ti-qspi",
|
|
.owner = THIS_MODULE,
|
|
.pm = &ti_qspi_pm_ops,
|
|
.of_match_table = ti_qspi_match,
|
|
}
|
|
};
|
|
|
|
module_platform_driver(ti_qspi_driver);
|
|
|
|
MODULE_AUTHOR("Sourav Poddar <sourav.poddar@ti.com>");
|
|
MODULE_LICENSE("GPL v2");
|
|
MODULE_DESCRIPTION("TI QSPI controller driver");
|
|
MODULE_ALIAS("platform:ti-qspi");
|