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c15def1cc3
The DB8500 ED (Early Drop) and V1 are only available inside of ST-Ericsson or partners, we have actively replaced and scrapped these prototypes. All Nova products on the open market (such as the Snowball board) are based on V2 and later ASIC variants. So let us focus on supporting the silicon that will be used and delete this to get a clear overview. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
187 lines
5.3 KiB
C
187 lines
5.3 KiB
C
/*
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* Copyright (C) ST-Ericsson SA 2010
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*
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* Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
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* License terms: GNU General Public License (GPL) version 2
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*/
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#include <linux/kernel.h>
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#include <linux/platform_device.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/gpio.h>
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#include <linux/amba/bus.h>
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#include <linux/amba/pl022.h>
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#include <plat/ste_dma40.h>
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#include <mach/hardware.h>
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#include <mach/setup.h>
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#include "ste-dma40-db8500.h"
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static struct resource dma40_resources[] = {
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[0] = {
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.start = U8500_DMA_BASE,
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.end = U8500_DMA_BASE + SZ_4K - 1,
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.flags = IORESOURCE_MEM,
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.name = "base",
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},
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[1] = {
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.start = U8500_DMA_LCPA_BASE,
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.end = U8500_DMA_LCPA_BASE + 2 * SZ_1K - 1,
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.flags = IORESOURCE_MEM,
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.name = "lcpa",
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},
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[2] = {
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.start = IRQ_DB8500_DMA,
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.end = IRQ_DB8500_DMA,
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.flags = IORESOURCE_IRQ,
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}
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};
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/* Default configuration for physcial memcpy */
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struct stedma40_chan_cfg dma40_memcpy_conf_phy = {
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.mode = STEDMA40_MODE_PHYSICAL,
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.dir = STEDMA40_MEM_TO_MEM,
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.src_info.data_width = STEDMA40_BYTE_WIDTH,
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.src_info.psize = STEDMA40_PSIZE_PHY_1,
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.src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
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.dst_info.data_width = STEDMA40_BYTE_WIDTH,
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.dst_info.psize = STEDMA40_PSIZE_PHY_1,
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.dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
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};
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/* Default configuration for logical memcpy */
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struct stedma40_chan_cfg dma40_memcpy_conf_log = {
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.dir = STEDMA40_MEM_TO_MEM,
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.src_info.data_width = STEDMA40_BYTE_WIDTH,
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.src_info.psize = STEDMA40_PSIZE_LOG_1,
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.src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
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.dst_info.data_width = STEDMA40_BYTE_WIDTH,
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.dst_info.psize = STEDMA40_PSIZE_LOG_1,
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.dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL,
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};
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/*
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* Mapping between destination event lines and physical device address.
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* The event line is tied to a device and therefore the address is constant.
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* When the address comes from a primecell it will be configured in runtime
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* and we set the address to -1 as a placeholder.
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*/
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static const dma_addr_t dma40_tx_map[DB8500_DMA_NR_DEV] = {
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/* MUSB - these will be runtime-reconfigured */
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[DB8500_DMA_DEV39_USB_OTG_OEP_8] = -1,
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[DB8500_DMA_DEV16_USB_OTG_OEP_7_15] = -1,
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[DB8500_DMA_DEV17_USB_OTG_OEP_6_14] = -1,
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[DB8500_DMA_DEV18_USB_OTG_OEP_5_13] = -1,
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[DB8500_DMA_DEV19_USB_OTG_OEP_4_12] = -1,
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[DB8500_DMA_DEV36_USB_OTG_OEP_3_11] = -1,
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[DB8500_DMA_DEV37_USB_OTG_OEP_2_10] = -1,
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[DB8500_DMA_DEV38_USB_OTG_OEP_1_9] = -1,
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/* PrimeCells - run-time configured */
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[DB8500_DMA_DEV0_SPI0_TX] = -1,
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[DB8500_DMA_DEV1_SD_MMC0_TX] = -1,
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[DB8500_DMA_DEV2_SD_MMC1_TX] = -1,
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[DB8500_DMA_DEV3_SD_MMC2_TX] = -1,
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[DB8500_DMA_DEV8_SSP0_TX] = -1,
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[DB8500_DMA_DEV9_SSP1_TX] = -1,
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[DB8500_DMA_DEV11_UART2_TX] = -1,
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[DB8500_DMA_DEV12_UART1_TX] = -1,
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[DB8500_DMA_DEV13_UART0_TX] = -1,
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[DB8500_DMA_DEV28_SD_MM2_TX] = -1,
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[DB8500_DMA_DEV29_SD_MM0_TX] = -1,
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[DB8500_DMA_DEV32_SD_MM1_TX] = -1,
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[DB8500_DMA_DEV33_SPI2_TX] = -1,
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[DB8500_DMA_DEV35_SPI1_TX] = -1,
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[DB8500_DMA_DEV40_SPI3_TX] = -1,
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[DB8500_DMA_DEV41_SD_MM3_TX] = -1,
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[DB8500_DMA_DEV42_SD_MM4_TX] = -1,
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[DB8500_DMA_DEV43_SD_MM5_TX] = -1,
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};
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/* Mapping between source event lines and physical device address */
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static const dma_addr_t dma40_rx_map[DB8500_DMA_NR_DEV] = {
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/* MUSB - these will be runtime-reconfigured */
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[DB8500_DMA_DEV39_USB_OTG_IEP_8] = -1,
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[DB8500_DMA_DEV16_USB_OTG_IEP_7_15] = -1,
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[DB8500_DMA_DEV17_USB_OTG_IEP_6_14] = -1,
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[DB8500_DMA_DEV18_USB_OTG_IEP_5_13] = -1,
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[DB8500_DMA_DEV19_USB_OTG_IEP_4_12] = -1,
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[DB8500_DMA_DEV36_USB_OTG_IEP_3_11] = -1,
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[DB8500_DMA_DEV37_USB_OTG_IEP_2_10] = -1,
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[DB8500_DMA_DEV38_USB_OTG_IEP_1_9] = -1,
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/* PrimeCells */
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[DB8500_DMA_DEV0_SPI0_RX] = -1,
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[DB8500_DMA_DEV1_SD_MMC0_RX] = -1,
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[DB8500_DMA_DEV2_SD_MMC1_RX] = -1,
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[DB8500_DMA_DEV3_SD_MMC2_RX] = -1,
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[DB8500_DMA_DEV8_SSP0_RX] = -1,
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[DB8500_DMA_DEV9_SSP1_RX] = -1,
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[DB8500_DMA_DEV11_UART2_RX] = -1,
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[DB8500_DMA_DEV12_UART1_RX] = -1,
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[DB8500_DMA_DEV13_UART0_RX] = -1,
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[DB8500_DMA_DEV28_SD_MM2_RX] = -1,
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[DB8500_DMA_DEV29_SD_MM0_RX] = -1,
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[DB8500_DMA_DEV32_SD_MM1_RX] = -1,
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[DB8500_DMA_DEV33_SPI2_RX] = -1,
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[DB8500_DMA_DEV35_SPI1_RX] = -1,
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[DB8500_DMA_DEV40_SPI3_RX] = -1,
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[DB8500_DMA_DEV41_SD_MM3_RX] = -1,
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[DB8500_DMA_DEV42_SD_MM4_RX] = -1,
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[DB8500_DMA_DEV43_SD_MM5_RX] = -1,
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};
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/* Reserved event lines for memcpy only */
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static int dma40_memcpy_event[] = {
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DB8500_DMA_MEMCPY_TX_0,
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DB8500_DMA_MEMCPY_TX_1,
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DB8500_DMA_MEMCPY_TX_2,
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DB8500_DMA_MEMCPY_TX_3,
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DB8500_DMA_MEMCPY_TX_4,
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DB8500_DMA_MEMCPY_TX_5,
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};
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static struct stedma40_platform_data dma40_plat_data = {
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.dev_len = DB8500_DMA_NR_DEV,
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.dev_rx = dma40_rx_map,
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.dev_tx = dma40_tx_map,
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.memcpy = dma40_memcpy_event,
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.memcpy_len = ARRAY_SIZE(dma40_memcpy_event),
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.memcpy_conf_phy = &dma40_memcpy_conf_phy,
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.memcpy_conf_log = &dma40_memcpy_conf_log,
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.disabled_channels = {-1},
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};
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struct platform_device u8500_dma40_device = {
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.dev = {
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.platform_data = &dma40_plat_data,
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},
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.name = "dma40",
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.id = 0,
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.num_resources = ARRAY_SIZE(dma40_resources),
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.resource = dma40_resources
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};
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struct resource keypad_resources[] = {
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[0] = {
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.start = U8500_SKE_BASE,
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.end = U8500_SKE_BASE + SZ_4K - 1,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = IRQ_DB8500_KB,
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.end = IRQ_DB8500_KB,
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.flags = IORESOURCE_IRQ,
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},
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};
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struct platform_device u8500_ske_keypad_device = {
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.name = "nmk-ske-keypad",
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.id = -1,
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.num_resources = ARRAY_SIZE(keypad_resources),
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.resource = keypad_resources,
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};
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