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![Robert Hancock](/assets/img/avatar_default.png)
This driver previously only handled the set_clkdiv divider callback when setting the SCLK Out Divider field in the I2S Timing Control register. However, when using the simple-audio-card driver, the set_sysclk function is called but not set_clkdiv. This caused the divider not to be set, leaving it at an invalid value of 0 and resulting in a very low SCLK output rate. Handle set_clkdiv and store the sysclk (MCLK) value for later use in hw_params to set the SCLK Out Divider such that: MCLK/SCLK = divider * 2 Signed-off-by: Robert Hancock <robert.hancock@calian.com> Link: https://lore.kernel.org/r/20220120195832.1742271-4-robert.hancock@calian.com Signed-off-by: Mark Brown <broonie@kernel.org>
257 lines
6.9 KiB
C
257 lines
6.9 KiB
C
// SPDX-License-Identifier: GPL-2.0
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//
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// Xilinx ASoC I2S audio support
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//
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// Copyright (C) 2018 Xilinx, Inc.
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//
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// Author: Praveen Vuppala <praveenv@xilinx.com>
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// Author: Maruthi Srinivas Bayyavarapu <maruthis@xilinx.com>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include <sound/pcm_params.h>
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#include <sound/soc.h>
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#define DRV_NAME "xlnx_i2s"
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#define I2S_CORE_CTRL_OFFSET 0x08
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#define I2S_CORE_CTRL_32BIT_LRCLK BIT(3)
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#define I2S_CORE_CTRL_ENABLE BIT(0)
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#define I2S_I2STIM_OFFSET 0x20
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#define I2S_CH0_OFFSET 0x30
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#define I2S_I2STIM_VALID_MASK GENMASK(7, 0)
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struct xlnx_i2s_drv_data {
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struct snd_soc_dai_driver dai_drv;
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void __iomem *base;
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unsigned int sysclk;
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u32 data_width;
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u32 channels;
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bool is_32bit_lrclk;
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struct snd_ratnum ratnum;
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struct snd_pcm_hw_constraint_ratnums rate_constraints;
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};
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static int xlnx_i2s_set_sclkout_div(struct snd_soc_dai *cpu_dai,
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int div_id, int div)
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{
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struct xlnx_i2s_drv_data *drv_data = snd_soc_dai_get_drvdata(cpu_dai);
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if (!div || (div & ~I2S_I2STIM_VALID_MASK))
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return -EINVAL;
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drv_data->sysclk = 0;
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writel(div, drv_data->base + I2S_I2STIM_OFFSET);
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return 0;
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}
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static int xlnx_i2s_set_sysclk(struct snd_soc_dai *dai,
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int clk_id, unsigned int freq, int dir)
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{
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struct xlnx_i2s_drv_data *drv_data = snd_soc_dai_get_drvdata(dai);
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drv_data->sysclk = freq;
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if (freq) {
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unsigned int bits_per_sample;
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if (drv_data->is_32bit_lrclk)
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bits_per_sample = 32;
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else
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bits_per_sample = drv_data->data_width;
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drv_data->ratnum.num = freq / (bits_per_sample * drv_data->channels) / 2;
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drv_data->ratnum.den_step = 1;
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drv_data->ratnum.den_min = 1;
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drv_data->ratnum.den_max = 255;
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drv_data->rate_constraints.rats = &drv_data->ratnum;
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drv_data->rate_constraints.nrats = 1;
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}
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return 0;
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}
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static int xlnx_i2s_startup(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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{
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struct xlnx_i2s_drv_data *drv_data = snd_soc_dai_get_drvdata(dai);
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if (drv_data->sysclk)
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return snd_pcm_hw_constraint_ratnums(substream->runtime, 0,
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SNDRV_PCM_HW_PARAM_RATE,
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&drv_data->rate_constraints);
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return 0;
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}
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static int xlnx_i2s_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params,
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struct snd_soc_dai *i2s_dai)
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{
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u32 reg_off, chan_id;
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struct xlnx_i2s_drv_data *drv_data = snd_soc_dai_get_drvdata(i2s_dai);
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if (drv_data->sysclk) {
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unsigned int bits_per_sample, sclk, sclk_div;
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if (drv_data->is_32bit_lrclk)
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bits_per_sample = 32;
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else
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bits_per_sample = drv_data->data_width;
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sclk = params_rate(params) * bits_per_sample * params_channels(params);
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sclk_div = drv_data->sysclk / sclk / 2;
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if ((drv_data->sysclk % sclk != 0) ||
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!sclk_div || (sclk_div & ~I2S_I2STIM_VALID_MASK)) {
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dev_warn(i2s_dai->dev, "invalid SCLK divisor for sysclk %u and sclk %u\n",
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drv_data->sysclk, sclk);
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return -EINVAL;
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}
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writel(sclk_div, drv_data->base + I2S_I2STIM_OFFSET);
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}
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chan_id = params_channels(params) / 2;
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while (chan_id > 0) {
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reg_off = I2S_CH0_OFFSET + ((chan_id - 1) * 4);
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writel(chan_id, drv_data->base + reg_off);
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chan_id--;
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}
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return 0;
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}
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static int xlnx_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
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struct snd_soc_dai *i2s_dai)
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{
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struct xlnx_i2s_drv_data *drv_data = snd_soc_dai_get_drvdata(i2s_dai);
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switch (cmd) {
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case SNDRV_PCM_TRIGGER_START:
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case SNDRV_PCM_TRIGGER_RESUME:
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case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
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writel(I2S_CORE_CTRL_ENABLE, drv_data->base + I2S_CORE_CTRL_OFFSET);
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break;
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case SNDRV_PCM_TRIGGER_STOP:
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case SNDRV_PCM_TRIGGER_SUSPEND:
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case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
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writel(0, drv_data->base + I2S_CORE_CTRL_OFFSET);
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static const struct snd_soc_dai_ops xlnx_i2s_dai_ops = {
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.trigger = xlnx_i2s_trigger,
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.set_sysclk = xlnx_i2s_set_sysclk,
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.set_clkdiv = xlnx_i2s_set_sclkout_div,
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.startup = xlnx_i2s_startup,
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.hw_params = xlnx_i2s_hw_params
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};
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static const struct snd_soc_component_driver xlnx_i2s_component = {
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.name = DRV_NAME,
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};
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static const struct of_device_id xlnx_i2s_of_match[] = {
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{ .compatible = "xlnx,i2s-transmitter-1.0", },
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{ .compatible = "xlnx,i2s-receiver-1.0", },
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{},
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};
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MODULE_DEVICE_TABLE(of, xlnx_i2s_of_match);
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static int xlnx_i2s_probe(struct platform_device *pdev)
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{
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struct xlnx_i2s_drv_data *drv_data;
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int ret;
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u32 format;
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struct device *dev = &pdev->dev;
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struct device_node *node = dev->of_node;
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drv_data = devm_kzalloc(&pdev->dev, sizeof(*drv_data), GFP_KERNEL);
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if (!drv_data)
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return -ENOMEM;
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drv_data->base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(drv_data->base))
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return PTR_ERR(drv_data->base);
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ret = of_property_read_u32(node, "xlnx,num-channels", &drv_data->channels);
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if (ret < 0) {
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dev_err(dev, "cannot get supported channels\n");
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return ret;
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}
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drv_data->channels *= 2;
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ret = of_property_read_u32(node, "xlnx,dwidth", &drv_data->data_width);
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if (ret < 0) {
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dev_err(dev, "cannot get data width\n");
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return ret;
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}
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switch (drv_data->data_width) {
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case 16:
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format = SNDRV_PCM_FMTBIT_S16_LE;
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break;
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case 24:
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format = SNDRV_PCM_FMTBIT_S24_LE;
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break;
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default:
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return -EINVAL;
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}
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if (of_device_is_compatible(node, "xlnx,i2s-transmitter-1.0")) {
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drv_data->dai_drv.name = "xlnx_i2s_playback";
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drv_data->dai_drv.playback.stream_name = "Playback";
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drv_data->dai_drv.playback.formats = format;
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drv_data->dai_drv.playback.channels_min = drv_data->channels;
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drv_data->dai_drv.playback.channels_max = drv_data->channels;
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drv_data->dai_drv.playback.rates = SNDRV_PCM_RATE_8000_192000;
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drv_data->dai_drv.ops = &xlnx_i2s_dai_ops;
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} else if (of_device_is_compatible(node, "xlnx,i2s-receiver-1.0")) {
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drv_data->dai_drv.name = "xlnx_i2s_capture";
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drv_data->dai_drv.capture.stream_name = "Capture";
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drv_data->dai_drv.capture.formats = format;
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drv_data->dai_drv.capture.channels_min = drv_data->channels;
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drv_data->dai_drv.capture.channels_max = drv_data->channels;
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drv_data->dai_drv.capture.rates = SNDRV_PCM_RATE_8000_192000;
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drv_data->dai_drv.ops = &xlnx_i2s_dai_ops;
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} else {
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return -ENODEV;
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}
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drv_data->is_32bit_lrclk = readl(drv_data->base + I2S_CORE_CTRL_OFFSET) &
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I2S_CORE_CTRL_32BIT_LRCLK;
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dev_set_drvdata(&pdev->dev, drv_data);
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ret = devm_snd_soc_register_component(&pdev->dev, &xlnx_i2s_component,
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&drv_data->dai_drv, 1);
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if (ret) {
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dev_err(&pdev->dev, "i2s component registration failed\n");
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return ret;
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}
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dev_info(&pdev->dev, "%s DAI registered\n", drv_data->dai_drv.name);
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return ret;
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}
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static struct platform_driver xlnx_i2s_aud_driver = {
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.driver = {
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.name = DRV_NAME,
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.of_match_table = xlnx_i2s_of_match,
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},
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.probe = xlnx_i2s_probe,
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};
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module_platform_driver(xlnx_i2s_aud_driver);
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MODULE_LICENSE("GPL v2");
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MODULE_AUTHOR("Praveen Vuppala <praveenv@xilinx.com>");
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MODULE_AUTHOR("Maruthi Srinivas Bayyavarapu <maruthis@xilinx.com>");
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