mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-09-27 12:57:53 +00:00
e5075d8ec5
This includes everything from part 2: * Support for tuning for systems with fast misaligned accesses. * Support for SBI-based suspend. * Support for the new SBI debug console extension. * The T-Head CMOs now use PA-based flushes. * Support for enabling the V extension in kernel code. * Optimized IP checksum routines. * Various ftrace improvements. * Support for archrandom, which depends on the Zkr extension. and then also a fix for those: * The build is no longer broken under NET=n, KUNIT=y for ports that don't define their own ipv6 checksum. -----BEGIN PGP SIGNATURE----- iQJHBAABCAAxFiEEKzw3R0RoQ7JKlDp6LhMZ81+7GIkFAmWsCOMTHHBhbG1lckBk YWJiZWx0LmNvbQAKCRAuExnzX7sYieQND/0f+1gizTM0OzuqZG9+DOdWTtqmILyr sZaYXWBw6SPzbUSlwjoW4Qp/S3Ur7IhrbfttM2aMoS4GHZvSESAXOMXC4c7AnCaQ HOXBC2OuXvq6jA0ZjK5XPviR70A/7uD2iu5SNO1hyfJK08LSEu+AulxtkW50+wMc bHXSpZxEf8AtwOJK1cRtwhH4qy+Qcs3Nla3jG7OnDsPbhJVcydHx95eCtfwn2cQA KwJPN1fjRtm4ALZb91QcMDO8VAoanfPEkSR3DoNVE/UfdTItYk35VHmf4RWh7IWA qDnV5Mp/XMX2RmJqwi1ZmSHHX0rfVLL5UqgBhGHC8PuMpLJn5p9U6DZ0qD7YWxcB NDlrHsaXt112RHEEM/7CcLkqEexua/ezcC45E5tSQ4sRDZE3fvgbALao67xSQ22D lCpVAY0Z3o5oWaM/jISiQHjSNn5RrAwEYSvvv2pkW4QAMShA2eggmQaCF+Jl4EMp u6yqJpXxDI99C088uvM6Bi2gcX8fnBSmOzCB/sSU4a1I72UpWrGngqUpTYKHG8Jz cTZhbIKmQirBP0vC/UgMOS0sNuw/NykItfRXZ2g0qGKvw1TjJ6djdeZBKcAj3h0E fJpMxuhmeOFYE7DavnhSt3CResFTXZzXLChjxGbT+g10YzVEf9g7vBVnjxAwad9f tryMVpL/ipGpQQ== =Sjhj -----END PGP SIGNATURE----- Merge tag 'riscv-for-linus-6.8-mw4' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux Pull more RISC-V updates from Palmer Dabbelt: - Support for tuning for systems with fast misaligned accesses. - Support for SBI-based suspend. - Support for the new SBI debug console extension. - The T-Head CMOs now use PA-based flushes. - Support for enabling the V extension in kernel code. - Optimized IP checksum routines. - Various ftrace improvements. - Support for archrandom, which depends on the Zkr extension. - The build is no longer broken under NET=n, KUNIT=y for ports that don't define their own ipv6 checksum. * tag 'riscv-for-linus-6.8-mw4' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (56 commits) lib: checksum: Fix build with CONFIG_NET=n riscv: lib: Check if output in asm goto supported riscv: Fix build error on rv32 + XIP riscv: optimize ELF relocation function in riscv RISC-V: Implement archrandom when Zkr is available riscv: Optimize hweight API with Zbb extension riscv: add dependency among Image(.gz), loader(.bin), and vmlinuz.efi samples: ftrace: Add RISC-V support for SAMPLE_FTRACE_DIRECT[_MULTI] riscv: ftrace: Add DYNAMIC_FTRACE_WITH_DIRECT_CALLS support riscv: ftrace: Make function graph use ftrace directly riscv: select FTRACE_MCOUNT_USE_PATCHABLE_FUNCTION_ENTRY lib/Kconfig.debug: Update AS_HAS_NON_CONST_LEB128 comment and name riscv: Restrict DWARF5 when building with LLVM to known working versions riscv: Hoist linker relaxation disabling logic into Kconfig kunit: Add tests for csum_ipv6_magic and ip_fast_csum riscv: Add checksum library riscv: Add checksum header riscv: Add static key for misaligned accesses asm-generic: Improve csum_fold RISC-V: selftests: cbo: Ensure asm operands match constraints ...
122 lines
3.7 KiB
Text
122 lines
3.7 KiB
Text
menu "CPU errata selection"
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config ERRATA_ANDES
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bool "Andes AX45MP errata"
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depends on RISCV_ALTERNATIVE && RISCV_SBI
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help
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All Andes errata Kconfig depend on this Kconfig. Disabling
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this Kconfig will disable all Andes errata. Please say "Y"
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here if your platform uses Andes CPU cores.
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Otherwise, please say "N" here to avoid unnecessary overhead.
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config ERRATA_ANDES_CMO
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bool "Apply Andes cache management errata"
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depends on ERRATA_ANDES && ARCH_R9A07G043
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select RISCV_DMA_NONCOHERENT
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default y
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help
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This will apply the cache management errata to handle the
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non-standard handling on non-coherent operations on Andes cores.
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If you don't know what to do here, say "Y".
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config ERRATA_SIFIVE
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bool "SiFive errata"
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depends on RISCV_ALTERNATIVE
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help
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All SiFive errata Kconfig depend on this Kconfig. Disabling
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this Kconfig will disable all SiFive errata. Please say "Y"
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here if your platform uses SiFive CPU cores.
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Otherwise, please say "N" here to avoid unnecessary overhead.
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config ERRATA_SIFIVE_CIP_453
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bool "Apply SiFive errata CIP-453"
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depends on ERRATA_SIFIVE && 64BIT
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default y
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help
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This will apply the SiFive CIP-453 errata to add sign extension
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to the $badaddr when exception type is instruction page fault
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and instruction access fault.
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If you don't know what to do here, say "Y".
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config ERRATA_SIFIVE_CIP_1200
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bool "Apply SiFive errata CIP-1200"
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depends on ERRATA_SIFIVE && 64BIT
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default y
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help
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This will apply the SiFive CIP-1200 errata to repalce all
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"sfence.vma addr" with "sfence.vma" to ensure that the addr
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has been flushed from TLB.
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If you don't know what to do here, say "Y".
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config ERRATA_STARFIVE_JH7100
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bool "StarFive JH7100 support"
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depends on ARCH_STARFIVE
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depends on !DMA_DIRECT_REMAP
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depends on NONPORTABLE
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select DMA_GLOBAL_POOL
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select RISCV_DMA_NONCOHERENT
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select RISCV_NONSTANDARD_CACHE_OPS
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select SIFIVE_CCACHE
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default n
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help
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The StarFive JH7100 was a test chip for the JH7110 and has
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caches that are non-coherent with respect to peripheral DMAs.
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It was designed before the Zicbom extension so needs non-standard
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cache operations through the SiFive cache controller.
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Say "Y" if you want to support the BeagleV Starlight and/or
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StarFive VisionFive V1 boards.
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config ERRATA_THEAD
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bool "T-HEAD errata"
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depends on RISCV_ALTERNATIVE
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help
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All T-HEAD errata Kconfig depend on this Kconfig. Disabling
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this Kconfig will disable all T-HEAD errata. Please say "Y"
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here if your platform uses T-HEAD CPU cores.
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Otherwise, please say "N" here to avoid unnecessary overhead.
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config ERRATA_THEAD_PBMT
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bool "Apply T-Head memory type errata"
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depends on ERRATA_THEAD && 64BIT && MMU
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select RISCV_ALTERNATIVE_EARLY
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default y
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help
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This will apply the memory type errata to handle the non-standard
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memory type bits in page-table-entries on T-Head SoCs.
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If you don't know what to do here, say "Y".
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config ERRATA_THEAD_CMO
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bool "Apply T-Head cache management errata"
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depends on ERRATA_THEAD && MMU
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select DMA_DIRECT_REMAP
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select RISCV_DMA_NONCOHERENT
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select RISCV_NONSTANDARD_CACHE_OPS
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default y
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help
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This will apply the cache management errata to handle the
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non-standard handling on non-coherent operations on T-Head SoCs.
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If you don't know what to do here, say "Y".
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config ERRATA_THEAD_PMU
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bool "Apply T-Head PMU errata"
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depends on ERRATA_THEAD && RISCV_PMU_SBI
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default y
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help
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The T-Head C9xx cores implement a PMU overflow extension very
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similar to the core SSCOFPMF extension.
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This will apply the overflow errata to handle the non-standard
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behaviour via the regular SBI PMU driver and interface.
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If you don't know what to do here, say "Y".
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endmenu # "CPU errata selection"
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