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38f5bd23de
There are no standard CSR registers to provide cache information, the way for RISC-V is to get this information from DT. Currently, AT_L1I_X, AT_L1D_X and AT_L2_X are present in glibc header, and sysconf syscall could use them to get information of cache through AUX vector. The result of 'getconf -a' as follows: LEVEL1_ICACHE_SIZE 32768 LEVEL1_ICACHE_ASSOC 8 LEVEL1_ICACHE_LINESIZE 64 LEVEL1_DCACHE_SIZE 32768 LEVEL1_DCACHE_ASSOC 8 LEVEL1_DCACHE_LINESIZE 64 LEVEL2_CACHE_SIZE 2097152 LEVEL2_CACHE_ASSOC 32 LEVEL2_CACHE_LINESIZE 64 Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Reviewed-by: Pekka Enberg <penberg@kernel.org> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
20 lines
511 B
C
20 lines
511 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2020 SiFive
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*/
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#ifndef _ASM_RISCV_CACHEINFO_H
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#define _ASM_RISCV_CACHEINFO_H
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#include <linux/cacheinfo.h>
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struct riscv_cacheinfo_ops {
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const struct attribute_group * (*get_priv_group)(struct cacheinfo
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*this_leaf);
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};
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void riscv_set_cacheinfo_ops(struct riscv_cacheinfo_ops *ops);
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uintptr_t get_cache_size(u32 level, enum cache_type type);
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uintptr_t get_cache_geometry(u32 level, enum cache_type type);
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#endif /* _ASM_RISCV_CACHEINFO_H */
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