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Per RISC-V semihosting spec [1], implement semihost.h for the existing Arm semihosting earlycon driver to work on RISC-V. Link: https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc [1] Signed-off-by: Bin Meng <bmeng@tinylab.org> Tested-by: Sergey Matyukevich <sergey.matyukevich@syntacore.com> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Link: https://lore.kernel.org/r/20221209150437.795918-3-bmeng@tinylab.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
26 lines
596 B
C
26 lines
596 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2022 tinylab.org
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* Author: Bin Meng <bmeng@tinylab.org>
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*/
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#ifndef _RISCV_SEMIHOST_H_
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#define _RISCV_SEMIHOST_H_
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struct uart_port;
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static inline void smh_putc(struct uart_port *port, unsigned char c)
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{
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asm volatile("addi a1, %0, 0\n"
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"addi a0, zero, 3\n"
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".balign 16\n"
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".option push\n"
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".option norvc\n"
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"slli zero, zero, 0x1f\n"
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"ebreak\n"
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"srai zero, zero, 0x7\n"
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".option pop\n"
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: : "r" (&c) : "a0", "a1", "memory");
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}
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#endif /* _RISCV_SEMIHOST_H_ */
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