Alexandru Elisei 96275c8f6c KVM: arm64: Don't zero the cycle count register when PMCR_EL0.P is set ... [ Upstream commit 2a71fabf6a ] According to ARM DDI 0487G.a, page D13-3895, setting the PMCR_EL0.P bit to 1 has the following effect: "Reset all event counters accessible in the current Exception level, not including PMCCNTR_EL0, to zero." Similar behaviour is described for AArch32 on page G8-7022. Make it so. Fixes: c01d6a1802 ("KVM: arm64: pmu: Only handle supported event counters") Signed-off-by: Alexandru Elisei <alexandru.elisei@arm.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20210618105139.83795-1-alexandru.elisei@arm.com Signed-off-by: Sasha Levin <sashal@kernel.org>		2021-07-14 16:56:08 +02:00
..
boot	arm64: dts: freescale: sl28: var4: fix RGMII clock and voltage	2021-06-10 13:39:22 +02:00
configs	arm64: defconfig: Build in CONFIG_GPIO_MXC by default	2020-10-26 15:48:58 +08:00
crypto	crypto: poly1305 - fix poly1305_core_setkey() declaration	2021-05-14 09:50:13 +02:00
include	arm64/mm: Fix ttbr0 values stored in struct thread_info for software-pan	2021-07-14 16:56:07 +02:00
kernel	arm64/mm: Fix ttbr0 values stored in struct thread_info for software-pan	2021-07-14 16:56:07 +02:00
kvm	KVM: arm64: Don't zero the cycle count register when PMCR_EL0.P is set	2021-07-14 16:56:08 +02:00
lib	arm64: Change .weak to SYM_FUNC_START_WEAK_PI for arch/arm64/lib/mem*.S	2020-10-30 08:32:31 +00:00
mm	arm64: consistently use reserved_pg_dir	2021-07-14 16:56:06 +02:00
net	arm64: bpf: Fix branch offset in JIT	2020-09-17 12:05:36 +01:00
xen
Kbuild
Kconfig	arm64: mte: Ensure TIF_MTE_ASYNC_FAULT is set atomically	2021-04-21 13:01:00 +02:00
Kconfig.debug	arm64: remove TEXT_OFFSET randomization	2020-06-15 13:10:59 +01:00
Kconfig.platforms	arm64: berlin: Select DW_APB_TIMER_OF	2020-10-26 10:45:03 +01:00
Makefile	arm64: link with -z norelro for LLD or aarch64-elf	2021-01-12 20:18:24 +01:00