Richard Weinberger 9661524b9b SPI NOR core changes: ... - move SECT_4K_PMC flag out of the core as it's a vendor specific flag - s/addr_width/addr_nbytes: address width means the number of IO lines used for the address, whereas in the code it is used as the number of address bytes. - do not change nor->addr_nbytes at SFDP parsing time. At the SFDP parsing time we should not change members of struct spi_nor, but instead fill members of struct spi_nor_flash_parameters which could later on be used by the callers. - track flash's internal address mode so that we can use 4B opcodes together with opcodes that don't have a 4B opcode correspondent. SPI NOR manufacturer drivers changes: - esmt: Rename "f25l32qa" flash name to "f25l32qa-2s". - micron-st: Skip FSR reading if SPI controller does not support it to allow flashes that support FSR to work even when attached to such SPI controllers. - spansion: Add s25hl-t/s25hs-t IDs and fixups. -----BEGIN PGP SIGNATURE----- iQEzBAABCgAdFiEEHUIqys8OyG1eHf7fS1VPR6WNFOkFAmLjfRkACgkQS1VPR6WN FOn9BQf/bCkxIpGY64RoV5CLNuDj+d4nAlqa7YaL7ftkHvgpEJd8x540dWxYnTsW FzOReFnZRtb4yjFAlOmYyqYhFuhWjDV4fmjWkeZwLqNM4GN80wKF3btf4V06gp5S Levjgmqiz/qBsrz9QYdDcB8YLVMOgInQLV8fNrBaG2oLAdskrzXaAukzkmvwnrHM iVQFZVLfP20qJOnoeahGJ7QObx2A8E9B2APXl9lOCTiVwuDwbFhkKQ3Vf7EqeOS1 BTwSRplAia/JvV+AsESQIL7C4I/xjDbIQ/UD9XsWD7yHo7f8FNi0fxrQ+j8HSnz9 49Ho+csCSV3MMqwnzQT6ciDzzd2zag== =MJ3w -----END PGP SIGNATURE----- Merge tag 'spi-nor/for-5.20' into mtd/next SPI NOR core changes: - move SECT_4K_PMC flag out of the core as it's a vendor specific flag - s/addr_width/addr_nbytes: address width means the number of IO lines used for the address, whereas in the code it is used as the number of address bytes. - do not change nor->addr_nbytes at SFDP parsing time. At the SFDP parsing time we should not change members of struct spi_nor, but instead fill members of struct spi_nor_flash_parameters which could later on be used by the callers. - track flash's internal address mode so that we can use 4B opcodes together with opcodes that don't have a 4B opcode correspondent. SPI NOR manufacturer drivers changes: - esmt: Rename "f25l32qa" flash name to "f25l32qa-2s". - micron-st: Skip FSR reading if SPI controller does not support it to allow flashes that support FSR to work even when attached to such SPI controllers. - spansion: Add s25hl-t/s25hs-t IDs and fixups.		2022-08-01 21:31:22 +02:00
..
bbm.h
blktrans.h
cfi.h	mtd: cfi_cmdset_0002: Use chip_ready() for write on S29GL064N	2022-04-28 10:17:10 +02:00
cfi_endian.h
concat.h
doc2000.h
flashchip.h
ftl.h
gen_probe.h
hyperbus.h	mtd: hyperbus: Make hyperbus_unregister_device() return void	2022-06-09 15:06:13 +02:00
inftl.h
jedec.h
lpc32xx_mlc.h
lpc32xx_slc.h
map.h
mtd.h	mtd: fix 'part' field data corruption in mtd_info	2022-04-21 09:29:05 +02:00
mtdram.h
nand-ecc-mtk.h	mtd: nand: make mtk_ecc.c a separated module	2022-04-27 18:12:35 +02:00
nand-ecc-mxic.h
nand-ecc-sw-bch.h
nand-ecc-sw-hamming.h
nand-gpio.h
nand.h
ndfc.h
nftl.h
onenand.h
onenand_regs.h
onfi.h
partitions.h
pfow.h
physmap.h
pismo.h
plat-ram.h
platnand.h
qinfo.h
rawnand.h
sh_flctl.h
sharpsl.h
spear_smi.h
spi-nor.h	mtd: spi-nor: s/addr_width/addr_nbytes	2022-07-28 05:11:56 +03:00
spinand.h	mtd: spinand: Add support for ATO25D1GA	2022-06-06 15:05:33 +02:00
super.h
ubi.h
xip.h