James Hogan 5fa393c857 MIPS: Break down cacheops.h definitions ... Most of the cache op codes defined in cacheops.h are split into a 2-bit cache identifier, and a 3-bit cache op code which does largely the same thing semantically regardless of the cache identifier. To allow the use of these definitions by KVM for decoding cache ops, break the definitions down into parts where it makes sense to do so, and add masks for the Cache and Op field within the cache op. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Gleb Natapov <gleb@kernel.org> Cc: kvm@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/11892/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>		2016-01-24 03:29:58 +01:00
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asm	MIPS: Break down cacheops.h definitions	2016-01-24 03:29:58 +01:00
uapi/asm	MIPS: inst.h: Fix some instruction descriptions	2016-01-24 01:36:50 +01:00