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Many processor architectures have no 64-bit atomic instructions, but we need atomic64_t in order to support the perf_counter subsystem. This adds an implementation of 64-bit atomic operations using hashed spinlocks to provide atomicity. For each atomic operation, the address of the atomic64_t variable is hashed to an index into an array of 16 spinlocks. That spinlock is taken (with interrupts disabled) around the operation, which can then be coded non-atomically within the lock. On UP, all the spinlock manipulation goes away and we simply disable interrupts around each operation. In fact gcc eliminates the whole atomic64_lock variable as well. Signed-off-by: Paul Mackerras <paulus@samba.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
175 lines
3.8 KiB
C
175 lines
3.8 KiB
C
/*
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* Generic implementation of 64-bit atomics using spinlocks,
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* useful on processors that don't have 64-bit atomic instructions.
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*
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* Copyright © 2009 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/types.h>
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#include <linux/cache.h>
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#include <linux/spinlock.h>
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#include <linux/init.h>
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#include <asm/atomic.h>
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/*
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* We use a hashed array of spinlocks to provide exclusive access
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* to each atomic64_t variable. Since this is expected to used on
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* systems with small numbers of CPUs (<= 4 or so), we use a
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* relatively small array of 16 spinlocks to avoid wasting too much
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* memory on the spinlock array.
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*/
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#define NR_LOCKS 16
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/*
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* Ensure each lock is in a separate cacheline.
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*/
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static union {
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spinlock_t lock;
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char pad[L1_CACHE_BYTES];
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} atomic64_lock[NR_LOCKS] __cacheline_aligned_in_smp;
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static inline spinlock_t *lock_addr(const atomic64_t *v)
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{
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unsigned long addr = (unsigned long) v;
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addr >>= L1_CACHE_SHIFT;
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addr ^= (addr >> 8) ^ (addr >> 16);
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return &atomic64_lock[addr & (NR_LOCKS - 1)].lock;
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}
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long long atomic64_read(const atomic64_t *v)
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{
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unsigned long flags;
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spinlock_t *lock = lock_addr(v);
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long long val;
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spin_lock_irqsave(lock, flags);
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val = v->counter;
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spin_unlock_irqrestore(lock, flags);
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return val;
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}
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void atomic64_set(atomic64_t *v, long long i)
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{
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unsigned long flags;
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spinlock_t *lock = lock_addr(v);
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spin_lock_irqsave(lock, flags);
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v->counter = i;
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spin_unlock_irqrestore(lock, flags);
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}
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void atomic64_add(long long a, atomic64_t *v)
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{
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unsigned long flags;
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spinlock_t *lock = lock_addr(v);
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spin_lock_irqsave(lock, flags);
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v->counter += a;
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spin_unlock_irqrestore(lock, flags);
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}
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long long atomic64_add_return(long long a, atomic64_t *v)
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{
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unsigned long flags;
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spinlock_t *lock = lock_addr(v);
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long long val;
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spin_lock_irqsave(lock, flags);
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val = v->counter += a;
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spin_unlock_irqrestore(lock, flags);
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return val;
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}
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void atomic64_sub(long long a, atomic64_t *v)
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{
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unsigned long flags;
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spinlock_t *lock = lock_addr(v);
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spin_lock_irqsave(lock, flags);
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v->counter -= a;
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spin_unlock_irqrestore(lock, flags);
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}
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long long atomic64_sub_return(long long a, atomic64_t *v)
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{
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unsigned long flags;
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spinlock_t *lock = lock_addr(v);
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long long val;
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spin_lock_irqsave(lock, flags);
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val = v->counter -= a;
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spin_unlock_irqrestore(lock, flags);
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return val;
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}
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long long atomic64_dec_if_positive(atomic64_t *v)
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{
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unsigned long flags;
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spinlock_t *lock = lock_addr(v);
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long long val;
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spin_lock_irqsave(lock, flags);
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val = v->counter - 1;
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if (val >= 0)
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v->counter = val;
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spin_unlock_irqrestore(lock, flags);
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return val;
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}
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long long atomic64_cmpxchg(atomic64_t *v, long long o, long long n)
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{
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unsigned long flags;
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spinlock_t *lock = lock_addr(v);
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long long val;
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spin_lock_irqsave(lock, flags);
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val = v->counter;
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if (val == o)
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v->counter = n;
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spin_unlock_irqrestore(lock, flags);
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return val;
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}
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long long atomic64_xchg(atomic64_t *v, long long new)
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{
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unsigned long flags;
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spinlock_t *lock = lock_addr(v);
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long long val;
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spin_lock_irqsave(lock, flags);
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val = v->counter;
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v->counter = new;
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spin_unlock_irqrestore(lock, flags);
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return val;
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}
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int atomic64_add_unless(atomic64_t *v, long long a, long long u)
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{
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unsigned long flags;
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spinlock_t *lock = lock_addr(v);
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int ret = 1;
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spin_lock_irqsave(lock, flags);
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if (v->counter != u) {
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v->counter += a;
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ret = 0;
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}
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spin_unlock_irqrestore(lock, flags);
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return ret;
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}
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static int init_atomic64_lock(void)
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{
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int i;
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for (i = 0; i < NR_LOCKS; ++i)
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spin_lock_init(&atomic64_lock[i].lock);
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return 0;
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}
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pure_initcall(init_atomic64_lock);
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