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2874c5fd28
Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 3029 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070032.746973796@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
198 lines
4.6 KiB
ArmAsm
198 lines
4.6 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright (C) 2015 Imagination Technologies
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* Author: Paul Burton <paul.burton@mips.com>
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*/
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#include <asm/addrspace.h>
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#include <asm/asm.h>
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#include <asm/asm-offsets.h>
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#include <asm/mipsregs.h>
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#include <asm/regdef.h>
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#include <linux/serial_reg.h>
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#define UART_TX_OFS (UART_TX << CONFIG_MIPS_CPS_NS16550_SHIFT)
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#define UART_LSR_OFS (UART_LSR << CONFIG_MIPS_CPS_NS16550_SHIFT)
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/**
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* _mips_cps_putc() - write a character to the UART
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* @a0: ASCII character to write
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* @t9: UART base address
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*/
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LEAF(_mips_cps_putc)
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1: lw t0, UART_LSR_OFS(t9)
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andi t0, t0, UART_LSR_TEMT
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beqz t0, 1b
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sb a0, UART_TX_OFS(t9)
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jr ra
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END(_mips_cps_putc)
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/**
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* _mips_cps_puts() - write a string to the UART
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* @a0: pointer to NULL-terminated ASCII string
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* @t9: UART base address
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*
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* Write a null-terminated ASCII string to the UART.
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*/
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NESTED(_mips_cps_puts, 0, ra)
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move s7, ra
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move s6, a0
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1: lb a0, 0(s6)
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beqz a0, 2f
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jal _mips_cps_putc
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PTR_ADDIU s6, s6, 1
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b 1b
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2: jr s7
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END(_mips_cps_puts)
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/**
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* _mips_cps_putx4 - write a 4b hex value to the UART
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* @a0: the 4b value to write to the UART
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* @t9: UART base address
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*
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* Write a single hexadecimal character to the UART.
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*/
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NESTED(_mips_cps_putx4, 0, ra)
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andi a0, a0, 0xf
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li t0, '0'
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blt a0, 10, 1f
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li t0, 'a'
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addiu a0, a0, -10
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1: addu a0, a0, t0
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b _mips_cps_putc
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END(_mips_cps_putx4)
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/**
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* _mips_cps_putx8 - write an 8b hex value to the UART
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* @a0: the 8b value to write to the UART
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* @t9: UART base address
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*
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* Write an 8 bit value (ie. 2 hexadecimal characters) to the UART.
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*/
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NESTED(_mips_cps_putx8, 0, ra)
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move s3, ra
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move s2, a0
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srl a0, a0, 4
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jal _mips_cps_putx4
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move a0, s2
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move ra, s3
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b _mips_cps_putx4
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END(_mips_cps_putx8)
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/**
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* _mips_cps_putx16 - write a 16b hex value to the UART
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* @a0: the 16b value to write to the UART
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* @t9: UART base address
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*
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* Write a 16 bit value (ie. 4 hexadecimal characters) to the UART.
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*/
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NESTED(_mips_cps_putx16, 0, ra)
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move s5, ra
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move s4, a0
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srl a0, a0, 8
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jal _mips_cps_putx8
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move a0, s4
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move ra, s5
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b _mips_cps_putx8
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END(_mips_cps_putx16)
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/**
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* _mips_cps_putx32 - write a 32b hex value to the UART
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* @a0: the 32b value to write to the UART
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* @t9: UART base address
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*
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* Write a 32 bit value (ie. 8 hexadecimal characters) to the UART.
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*/
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NESTED(_mips_cps_putx32, 0, ra)
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move s7, ra
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move s6, a0
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srl a0, a0, 16
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jal _mips_cps_putx16
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move a0, s6
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move ra, s7
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b _mips_cps_putx16
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END(_mips_cps_putx32)
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#ifdef CONFIG_64BIT
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/**
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* _mips_cps_putx64 - write a 64b hex value to the UART
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* @a0: the 64b value to write to the UART
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* @t9: UART base address
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*
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* Write a 64 bit value (ie. 16 hexadecimal characters) to the UART.
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*/
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NESTED(_mips_cps_putx64, 0, ra)
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move sp, ra
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move s8, a0
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dsrl32 a0, a0, 0
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jal _mips_cps_putx32
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move a0, s8
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move ra, sp
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b _mips_cps_putx32
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END(_mips_cps_putx64)
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#define _mips_cps_putxlong _mips_cps_putx64
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#else /* !CONFIG_64BIT */
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#define _mips_cps_putxlong _mips_cps_putx32
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#endif /* !CONFIG_64BIT */
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/**
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* mips_cps_bev_dump() - dump relevant exception state to UART
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* @a0: pointer to NULL-terminated ASCII string naming the exception
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*
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* Write information that may be useful in debugging an exception to the
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* UART configured by CONFIG_MIPS_CPS_NS16550_*. As this BEV exception
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* will only be run if something goes horribly wrong very early during
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* the bringup of a core and it is very likely to be unsafe to perform
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* memory accesses at that point (cache state indeterminate, EVA may not
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* be configured, coherence may be disabled) let alone have a stack,
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* this is all written in assembly using only registers & unmapped
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* uncached access to the UART registers.
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*/
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LEAF(mips_cps_bev_dump)
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move s0, ra
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move s1, a0
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li t9, CKSEG1ADDR(CONFIG_MIPS_CPS_NS16550_BASE)
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PTR_LA a0, str_newline
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jal _mips_cps_puts
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PTR_LA a0, str_bev
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jal _mips_cps_puts
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move a0, s1
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jal _mips_cps_puts
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PTR_LA a0, str_newline
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jal _mips_cps_puts
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PTR_LA a0, str_newline
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jal _mips_cps_puts
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#define DUMP_COP0_REG(reg, name, sz, _mfc0) \
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PTR_LA a0, 8f; \
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jal _mips_cps_puts; \
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_mfc0 a0, reg; \
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jal _mips_cps_putx##sz; \
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PTR_LA a0, str_newline; \
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jal _mips_cps_puts; \
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TEXT(name)
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DUMP_COP0_REG(CP0_CAUSE, "Cause: 0x", 32, mfc0)
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DUMP_COP0_REG(CP0_STATUS, "Status: 0x", 32, mfc0)
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DUMP_COP0_REG(CP0_EBASE, "EBase: 0x", long, MFC0)
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DUMP_COP0_REG(CP0_BADVADDR, "BadVAddr: 0x", long, MFC0)
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DUMP_COP0_REG(CP0_BADINSTR, "BadInstr: 0x", 32, mfc0)
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PTR_LA a0, str_newline
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jal _mips_cps_puts
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jr s0
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END(mips_cps_bev_dump)
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.pushsection .data
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str_bev: .asciiz "BEV Exception: "
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str_newline: .asciiz "\r\n"
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.popsection
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