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![Thomas Gleixner](/assets/img/avatar_default.png)
Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 3029 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070032.746973796@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
323 lines
7.5 KiB
C
323 lines
7.5 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (C) 2003, 2004, 2007 Maciej W. Rozycki
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*/
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#include <linux/context_tracking.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/ptrace.h>
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#include <linux/stddef.h>
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#include <asm/bugs.h>
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#include <asm/compiler.h>
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#include <asm/cpu.h>
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#include <asm/fpu.h>
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#include <asm/mipsregs.h>
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#include <asm/setup.h>
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static char bug64hit[] __initdata =
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"reliable operation impossible!\n%s";
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static char nowar[] __initdata =
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"Please report to <linux-mips@linux-mips.org>.";
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static char r4kwar[] __initdata =
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"Enable CPU_R4000_WORKAROUNDS to rectify.";
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static char daddiwar[] __initdata =
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"Enable CPU_DADDI_WORKAROUNDS to rectify.";
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static inline void align_mod(const int align, const int mod)
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{
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asm volatile(
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".set push\n\t"
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".set noreorder\n\t"
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".balign %0\n\t"
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".rept %1\n\t"
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"nop\n\t"
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".endr\n\t"
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".set pop"
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:
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: "n"(align), "n"(mod));
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}
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static __always_inline void mult_sh_align_mod(long *v1, long *v2, long *w,
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const int align, const int mod)
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{
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unsigned long flags;
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int m1, m2;
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long p, s, lv1, lv2, lw;
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/*
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* We want the multiply and the shift to be isolated from the
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* rest of the code to disable gcc optimizations. Hence the
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* asm statements that execute nothing, but make gcc not know
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* what the values of m1, m2 and s are and what lv2 and p are
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* used for.
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*/
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local_irq_save(flags);
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/*
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* The following code leads to a wrong result of the first
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* dsll32 when executed on R4000 rev. 2.2 or 3.0 (PRId
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* 00000422 or 00000430, respectively).
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*
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* See "MIPS R4000PC/SC Errata, Processor Revision 2.2 and
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* 3.0" by MIPS Technologies, Inc., errata #16 and #28 for
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* details. I got no permission to duplicate them here,
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* sigh... --macro
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*/
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asm volatile(
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""
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: "=r" (m1), "=r" (m2), "=r" (s)
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: "0" (5), "1" (8), "2" (5));
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align_mod(align, mod);
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/*
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* The trailing nop is needed to fulfill the two-instruction
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* requirement between reading hi/lo and staring a mult/div.
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* Leaving it out may cause gas insert a nop itself breaking
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* the desired alignment of the next chunk.
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*/
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asm volatile(
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".set push\n\t"
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".set noat\n\t"
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".set noreorder\n\t"
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".set nomacro\n\t"
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"mult %2, %3\n\t"
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"dsll32 %0, %4, %5\n\t"
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"mflo $0\n\t"
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"dsll32 %1, %4, %5\n\t"
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"nop\n\t"
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".set pop"
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: "=&r" (lv1), "=r" (lw)
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: "r" (m1), "r" (m2), "r" (s), "I" (0)
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: "hi", "lo", "$0");
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/* We have to use single integers for m1 and m2 and a double
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* one for p to be sure the mulsidi3 gcc's RTL multiplication
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* instruction has the workaround applied. Older versions of
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* gcc have correct umulsi3 and mulsi3, but other
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* multiplication variants lack the workaround.
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*/
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asm volatile(
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""
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: "=r" (m1), "=r" (m2), "=r" (s)
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: "0" (m1), "1" (m2), "2" (s));
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align_mod(align, mod);
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p = m1 * m2;
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lv2 = s << 32;
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asm volatile(
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""
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: "=r" (lv2)
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: "0" (lv2), "r" (p));
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local_irq_restore(flags);
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*v1 = lv1;
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*v2 = lv2;
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*w = lw;
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}
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static inline void check_mult_sh(void)
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{
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long v1[8], v2[8], w[8];
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int bug, fix, i;
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printk("Checking for the multiply/shift bug... ");
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/*
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* Testing discovered false negatives for certain code offsets
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* into cache lines. Hence we test all possible offsets for
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* the worst assumption of an R4000 I-cache line width of 32
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* bytes.
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*
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* We can't use a loop as alignment directives need to be
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* immediates.
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*/
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mult_sh_align_mod(&v1[0], &v2[0], &w[0], 32, 0);
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mult_sh_align_mod(&v1[1], &v2[1], &w[1], 32, 1);
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mult_sh_align_mod(&v1[2], &v2[2], &w[2], 32, 2);
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mult_sh_align_mod(&v1[3], &v2[3], &w[3], 32, 3);
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mult_sh_align_mod(&v1[4], &v2[4], &w[4], 32, 4);
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mult_sh_align_mod(&v1[5], &v2[5], &w[5], 32, 5);
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mult_sh_align_mod(&v1[6], &v2[6], &w[6], 32, 6);
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mult_sh_align_mod(&v1[7], &v2[7], &w[7], 32, 7);
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bug = 0;
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for (i = 0; i < 8; i++)
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if (v1[i] != w[i])
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bug = 1;
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if (bug == 0) {
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pr_cont("no.\n");
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return;
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}
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pr_cont("yes, workaround... ");
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fix = 1;
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for (i = 0; i < 8; i++)
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if (v2[i] != w[i])
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fix = 0;
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if (fix == 1) {
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pr_cont("yes.\n");
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return;
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}
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pr_cont("no.\n");
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panic(bug64hit, !R4000_WAR ? r4kwar : nowar);
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}
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static volatile int daddi_ov;
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asmlinkage void __init do_daddi_ov(struct pt_regs *regs)
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{
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enum ctx_state prev_state;
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prev_state = exception_enter();
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daddi_ov = 1;
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regs->cp0_epc += 4;
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exception_exit(prev_state);
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}
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static inline void check_daddi(void)
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{
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extern asmlinkage void handle_daddi_ov(void);
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unsigned long flags;
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void *handler;
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long v, tmp;
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printk("Checking for the daddi bug... ");
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local_irq_save(flags);
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handler = set_except_vector(EXCCODE_OV, handle_daddi_ov);
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/*
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* The following code fails to trigger an overflow exception
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* when executed on R4000 rev. 2.2 or 3.0 (PRId 00000422 or
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* 00000430, respectively).
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*
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* See "MIPS R4000PC/SC Errata, Processor Revision 2.2 and
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* 3.0" by MIPS Technologies, Inc., erratum #23 for details.
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* I got no permission to duplicate it here, sigh... --macro
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*/
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asm volatile(
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".set push\n\t"
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".set noat\n\t"
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".set noreorder\n\t"
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".set nomacro\n\t"
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"addiu %1, $0, %2\n\t"
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"dsrl %1, %1, 1\n\t"
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#ifdef HAVE_AS_SET_DADDI
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".set daddi\n\t"
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#endif
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"daddi %0, %1, %3\n\t"
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".set pop"
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: "=r" (v), "=&r" (tmp)
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: "I" (0xffffffffffffdb9aUL), "I" (0x1234));
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set_except_vector(EXCCODE_OV, handler);
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local_irq_restore(flags);
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if (daddi_ov) {
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pr_cont("no.\n");
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return;
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}
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pr_cont("yes, workaround... ");
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local_irq_save(flags);
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handler = set_except_vector(EXCCODE_OV, handle_daddi_ov);
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asm volatile(
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"addiu %1, $0, %2\n\t"
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"dsrl %1, %1, 1\n\t"
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"daddi %0, %1, %3"
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: "=r" (v), "=&r" (tmp)
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: "I" (0xffffffffffffdb9aUL), "I" (0x1234));
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set_except_vector(EXCCODE_OV, handler);
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local_irq_restore(flags);
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if (daddi_ov) {
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pr_cont("yes.\n");
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return;
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}
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pr_cont("no.\n");
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panic(bug64hit, !DADDI_WAR ? daddiwar : nowar);
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}
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int daddiu_bug = IS_ENABLED(CONFIG_CPU_MIPSR6) ? 0 : -1;
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static inline void check_daddiu(void)
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{
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long v, w, tmp;
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printk("Checking for the daddiu bug... ");
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/*
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* The following code leads to a wrong result of daddiu when
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* executed on R4400 rev. 1.0 (PRId 00000440).
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*
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* See "MIPS R4400PC/SC Errata, Processor Revision 1.0" by
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* MIPS Technologies, Inc., erratum #7 for details.
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*
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* According to "MIPS R4000PC/SC Errata, Processor Revision
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* 2.2 and 3.0" by MIPS Technologies, Inc., erratum #41 this
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* problem affects R4000 rev. 2.2 and 3.0 (PRId 00000422 and
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* 00000430, respectively), too. Testing failed to trigger it
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* so far.
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*
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* I got no permission to duplicate the errata here, sigh...
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* --macro
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*/
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asm volatile(
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".set push\n\t"
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".set noat\n\t"
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".set noreorder\n\t"
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".set nomacro\n\t"
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"addiu %2, $0, %3\n\t"
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"dsrl %2, %2, 1\n\t"
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#ifdef HAVE_AS_SET_DADDI
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".set daddi\n\t"
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#endif
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"daddiu %0, %2, %4\n\t"
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"addiu %1, $0, %4\n\t"
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"daddu %1, %2\n\t"
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".set pop"
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: "=&r" (v), "=&r" (w), "=&r" (tmp)
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: "I" (0xffffffffffffdb9aUL), "I" (0x1234));
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daddiu_bug = v != w;
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if (!daddiu_bug) {
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pr_cont("no.\n");
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return;
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}
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pr_cont("yes, workaround... ");
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asm volatile(
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"addiu %2, $0, %3\n\t"
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"dsrl %2, %2, 1\n\t"
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"daddiu %0, %2, %4\n\t"
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"addiu %1, $0, %4\n\t"
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"daddu %1, %2"
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: "=&r" (v), "=&r" (w), "=&r" (tmp)
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: "I" (0xffffffffffffdb9aUL), "I" (0x1234));
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if (v == w) {
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pr_cont("yes.\n");
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return;
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}
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pr_cont("no.\n");
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panic(bug64hit, !DADDI_WAR ? daddiwar : nowar);
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}
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void __init check_bugs64_early(void)
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{
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if (!IS_ENABLED(CONFIG_CPU_MIPSR6)) {
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check_mult_sh();
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check_daddiu();
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}
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}
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void __init check_bugs64(void)
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{
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if (!IS_ENABLED(CONFIG_CPU_MIPSR6))
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check_daddi();
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}
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