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![Linus Torvalds](/assets/img/avatar_default.png)
- Removal of readq & writeq for MIPS32 kernels where they would simply BUG() anyway, allowing drivers or other code that #ifdefs on their presence to work properly. - Improvements for Ingenic JZ4740 systems, including support for the external memory controller & pinmuxing fixes for qi_lb60/NanoNote systems. - Improvements for Lantiq systems, in particular around SMP & IPIs. - DT updates for ralink/MediaTek MT7628a systems to probe & configure a bunch more devices. - Miscellaneous cleanups & build fixes. -----BEGIN PGP SIGNATURE----- iIsEABYIADMWIQRgLjeFAZEXQzy86/s+p5+stXUA3QUCXS85dBUccGF1bC5idXJ0 b25AbWlwcy5jb20ACgkQPqefrLV1AN2yJwEA6SUzzTXdywxEy78Ala3tzghMjkD5 818q6a9DREGofyIA/ie08di/MIYS9++ETsaQemVXoe7KT333+SgTeXCb1lIJ =RiKE -----END PGP SIGNATURE----- Merge tag 'mips_5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux Pull MIPS updates from Paul Burton: "A light batch this time around but significant improvements for certain systems: - Removal of readq & writeq for MIPS32 kernels where they would simply BUG() anyway, allowing drivers or other code that #ifdefs on their presence to work properly. - Improvements for Ingenic JZ4740 systems, including support for the external memory controller & pinmuxing fixes for qi_lb60/NanoNote systems. - Improvements for Lantiq systems, in particular around SMP & IPIs. - DT updates for ralink/MediaTek MT7628a systems to probe & configure a bunch more devices. - Miscellaneous cleanups & build fixes" * tag 'mips_5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (30 commits) MIPS: fix some more fall through errors in arch/mips MIPS: perf events: handle switch statement falling through warnings mips/kprobes: Export kprobe_fault_handler() MAINTAINERS: Add myself as Ingenic SoCs maintainer MIPS: ralink: mt7628a.dtsi: Add watchdog controller DT node MIPS: ralink: mt7628a.dtsi: Add SPI controller DT node MIPS: ralink: mt7628a.dtsi: Add GPIO controller DT node MIPS: ralink: mt7628a.dtsi: Add pinctrl DT properties to the UART nodes MIPS: ralink: mt7628a.dtsi: Add pinmux DT node MIPS: ralink: mt7628a.dtsi: Add SPDX GPL-2.0 license identifier MIPS: lantiq: Add SMP support for lantiq interrupt controller MIPS: lantiq: Shorten register names, remove unused macros MIPS: lantiq: Fix bitfield masking MIPS: lantiq: Remove unused macros MIPS: lantiq: Fix attributes of of_device_id structure MIPS: lantiq: Change variables to the same type as the source MIPS: lantiq: Move macro directly to iomem function mips: Remove q-accessors from non-64bit platforms FDDI: defza: Include linux/io-64-nonatomic-lo-hi.h MIPS: configs: Remove useless UEVENT_HELPER_PATH ...
433 lines
10 KiB
C
433 lines
10 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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*
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* Copyright (C) 2010 John Crispin <john@phrozen.org>
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* Copyright (C) 2010 Thomas Langer <thomas.langer@lantiq.com>
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*/
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#include <linux/interrupt.h>
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#include <linux/ioport.h>
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#include <linux/sched.h>
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#include <linux/irqdomain.h>
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#include <linux/of_platform.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <asm/bootinfo.h>
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#include <asm/irq_cpu.h>
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#include <lantiq_soc.h>
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#include <irq.h>
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/* register definitions - internal irqs */
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#define LTQ_ICU_ISR 0x0000
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#define LTQ_ICU_IER 0x0008
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#define LTQ_ICU_IOSR 0x0010
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#define LTQ_ICU_IRSR 0x0018
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#define LTQ_ICU_IMR 0x0020
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#define LTQ_ICU_IM_SIZE 0x28
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/* register definitions - external irqs */
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#define LTQ_EIU_EXIN_C 0x0000
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#define LTQ_EIU_EXIN_INIC 0x0004
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#define LTQ_EIU_EXIN_INC 0x0008
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#define LTQ_EIU_EXIN_INEN 0x000C
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/* number of external interrupts */
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#define MAX_EIU 6
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/* the performance counter */
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#define LTQ_PERF_IRQ (INT_NUM_IM4_IRL0 + 31)
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/*
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* irqs generated by devices attached to the EBU need to be acked in
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* a special manner
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*/
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#define LTQ_ICU_EBU_IRQ 22
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#define ltq_icu_w32(vpe, m, x, y) \
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ltq_w32((x), ltq_icu_membase[vpe] + m*LTQ_ICU_IM_SIZE + (y))
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#define ltq_icu_r32(vpe, m, x) \
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ltq_r32(ltq_icu_membase[vpe] + m*LTQ_ICU_IM_SIZE + (x))
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#define ltq_eiu_w32(x, y) ltq_w32((x), ltq_eiu_membase + (y))
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#define ltq_eiu_r32(x) ltq_r32(ltq_eiu_membase + (x))
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/* we have a cascade of 8 irqs */
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#define MIPS_CPU_IRQ_CASCADE 8
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static int exin_avail;
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static u32 ltq_eiu_irq[MAX_EIU];
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static void __iomem *ltq_icu_membase[NR_CPUS];
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static void __iomem *ltq_eiu_membase;
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static struct irq_domain *ltq_domain;
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static DEFINE_SPINLOCK(ltq_eiu_lock);
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static DEFINE_RAW_SPINLOCK(ltq_icu_lock);
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static int ltq_perfcount_irq;
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int ltq_eiu_get_irq(int exin)
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{
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if (exin < exin_avail)
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return ltq_eiu_irq[exin];
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return -1;
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}
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void ltq_disable_irq(struct irq_data *d)
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{
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unsigned long offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
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unsigned long im = offset / INT_NUM_IM_OFFSET;
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unsigned long flags;
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int vpe;
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offset %= INT_NUM_IM_OFFSET;
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raw_spin_lock_irqsave(<q_icu_lock, flags);
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for_each_present_cpu(vpe) {
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ltq_icu_w32(vpe, im,
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ltq_icu_r32(vpe, im, LTQ_ICU_IER) & ~BIT(offset),
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LTQ_ICU_IER);
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}
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raw_spin_unlock_irqrestore(<q_icu_lock, flags);
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}
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void ltq_mask_and_ack_irq(struct irq_data *d)
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{
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unsigned long offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
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unsigned long im = offset / INT_NUM_IM_OFFSET;
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unsigned long flags;
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int vpe;
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offset %= INT_NUM_IM_OFFSET;
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raw_spin_lock_irqsave(<q_icu_lock, flags);
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for_each_present_cpu(vpe) {
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ltq_icu_w32(vpe, im,
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ltq_icu_r32(vpe, im, LTQ_ICU_IER) & ~BIT(offset),
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LTQ_ICU_IER);
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ltq_icu_w32(vpe, im, BIT(offset), LTQ_ICU_ISR);
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}
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raw_spin_unlock_irqrestore(<q_icu_lock, flags);
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}
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static void ltq_ack_irq(struct irq_data *d)
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{
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unsigned long offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
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unsigned long im = offset / INT_NUM_IM_OFFSET;
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unsigned long flags;
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int vpe;
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offset %= INT_NUM_IM_OFFSET;
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raw_spin_lock_irqsave(<q_icu_lock, flags);
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for_each_present_cpu(vpe) {
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ltq_icu_w32(vpe, im, BIT(offset), LTQ_ICU_ISR);
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}
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raw_spin_unlock_irqrestore(<q_icu_lock, flags);
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}
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void ltq_enable_irq(struct irq_data *d)
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{
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unsigned long offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
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unsigned long im = offset / INT_NUM_IM_OFFSET;
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unsigned long flags;
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int vpe;
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offset %= INT_NUM_IM_OFFSET;
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vpe = cpumask_first(irq_data_get_effective_affinity_mask(d));
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/* This shouldn't be even possible, maybe during CPU hotplug spam */
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if (unlikely(vpe >= nr_cpu_ids))
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vpe = smp_processor_id();
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raw_spin_lock_irqsave(<q_icu_lock, flags);
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ltq_icu_w32(vpe, im, ltq_icu_r32(vpe, im, LTQ_ICU_IER) | BIT(offset),
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LTQ_ICU_IER);
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raw_spin_unlock_irqrestore(<q_icu_lock, flags);
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}
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static int ltq_eiu_settype(struct irq_data *d, unsigned int type)
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{
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int i;
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unsigned long flags;
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for (i = 0; i < exin_avail; i++) {
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if (d->hwirq == ltq_eiu_irq[i]) {
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int val = 0;
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int edge = 0;
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switch (type) {
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case IRQF_TRIGGER_NONE:
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break;
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case IRQF_TRIGGER_RISING:
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val = 1;
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edge = 1;
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break;
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case IRQF_TRIGGER_FALLING:
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val = 2;
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edge = 1;
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break;
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case IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING:
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val = 3;
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edge = 1;
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break;
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case IRQF_TRIGGER_HIGH:
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val = 5;
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break;
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case IRQF_TRIGGER_LOW:
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val = 6;
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break;
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default:
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pr_err("invalid type %d for irq %ld\n",
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type, d->hwirq);
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return -EINVAL;
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}
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if (edge)
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irq_set_handler(d->hwirq, handle_edge_irq);
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spin_lock_irqsave(<q_eiu_lock, flags);
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ltq_eiu_w32((ltq_eiu_r32(LTQ_EIU_EXIN_C) &
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(~(7 << (i * 4)))) | (val << (i * 4)),
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LTQ_EIU_EXIN_C);
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spin_unlock_irqrestore(<q_eiu_lock, flags);
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}
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}
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return 0;
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}
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static unsigned int ltq_startup_eiu_irq(struct irq_data *d)
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{
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int i;
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ltq_enable_irq(d);
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for (i = 0; i < exin_avail; i++) {
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if (d->hwirq == ltq_eiu_irq[i]) {
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/* by default we are low level triggered */
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ltq_eiu_settype(d, IRQF_TRIGGER_LOW);
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/* clear all pending */
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ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INC) & ~BIT(i),
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LTQ_EIU_EXIN_INC);
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/* enable */
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ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INEN) | BIT(i),
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LTQ_EIU_EXIN_INEN);
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break;
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}
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}
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return 0;
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}
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static void ltq_shutdown_eiu_irq(struct irq_data *d)
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{
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int i;
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ltq_disable_irq(d);
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for (i = 0; i < exin_avail; i++) {
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if (d->hwirq == ltq_eiu_irq[i]) {
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/* disable */
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ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_INEN) & ~BIT(i),
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LTQ_EIU_EXIN_INEN);
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break;
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}
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}
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}
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#if defined(CONFIG_SMP)
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static int ltq_icu_irq_set_affinity(struct irq_data *d,
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const struct cpumask *cpumask, bool force)
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{
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struct cpumask tmask;
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if (!cpumask_and(&tmask, cpumask, cpu_online_mask))
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return -EINVAL;
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irq_data_update_effective_affinity(d, &tmask);
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return IRQ_SET_MASK_OK;
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}
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#endif
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static struct irq_chip ltq_irq_type = {
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.name = "icu",
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.irq_enable = ltq_enable_irq,
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.irq_disable = ltq_disable_irq,
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.irq_unmask = ltq_enable_irq,
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.irq_ack = ltq_ack_irq,
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.irq_mask = ltq_disable_irq,
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.irq_mask_ack = ltq_mask_and_ack_irq,
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#if defined(CONFIG_SMP)
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.irq_set_affinity = ltq_icu_irq_set_affinity,
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#endif
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};
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static struct irq_chip ltq_eiu_type = {
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.name = "eiu",
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.irq_startup = ltq_startup_eiu_irq,
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.irq_shutdown = ltq_shutdown_eiu_irq,
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.irq_enable = ltq_enable_irq,
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.irq_disable = ltq_disable_irq,
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.irq_unmask = ltq_enable_irq,
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.irq_ack = ltq_ack_irq,
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.irq_mask = ltq_disable_irq,
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.irq_mask_ack = ltq_mask_and_ack_irq,
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.irq_set_type = ltq_eiu_settype,
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#if defined(CONFIG_SMP)
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.irq_set_affinity = ltq_icu_irq_set_affinity,
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#endif
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};
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static void ltq_hw_irq_handler(struct irq_desc *desc)
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{
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unsigned int module = irq_desc_get_irq(desc) - 2;
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u32 irq;
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irq_hw_number_t hwirq;
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int vpe = smp_processor_id();
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irq = ltq_icu_r32(vpe, module, LTQ_ICU_IOSR);
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if (irq == 0)
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return;
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/*
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* silicon bug causes only the msb set to 1 to be valid. all
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* other bits might be bogus
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*/
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irq = __fls(irq);
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hwirq = irq + MIPS_CPU_IRQ_CASCADE + (INT_NUM_IM_OFFSET * module);
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generic_handle_irq(irq_linear_revmap(ltq_domain, hwirq));
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/* if this is a EBU irq, we need to ack it or get a deadlock */
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if ((irq == LTQ_ICU_EBU_IRQ) && (module == 0) && LTQ_EBU_PCC_ISTAT)
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ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_ISTAT) | 0x10,
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LTQ_EBU_PCC_ISTAT);
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}
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static int icu_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
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{
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struct irq_chip *chip = <q_irq_type;
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struct irq_data *data;
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int i;
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if (hw < MIPS_CPU_IRQ_CASCADE)
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return 0;
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for (i = 0; i < exin_avail; i++)
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if (hw == ltq_eiu_irq[i])
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chip = <q_eiu_type;
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data = irq_get_irq_data(irq);
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irq_data_update_effective_affinity(data, cpumask_of(0));
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irq_set_chip_and_handler(irq, chip, handle_level_irq);
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return 0;
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}
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static const struct irq_domain_ops irq_domain_ops = {
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.xlate = irq_domain_xlate_onetwocell,
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.map = icu_map,
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};
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int __init icu_of_init(struct device_node *node, struct device_node *parent)
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{
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struct device_node *eiu_node;
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struct resource res;
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int i, ret, vpe;
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/* load register regions of available ICUs */
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for_each_possible_cpu(vpe) {
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if (of_address_to_resource(node, vpe, &res))
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panic("Failed to get icu%i memory range", vpe);
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if (!request_mem_region(res.start, resource_size(&res),
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res.name))
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pr_err("Failed to request icu%i memory\n", vpe);
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ltq_icu_membase[vpe] = ioremap_nocache(res.start,
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resource_size(&res));
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if (!ltq_icu_membase[vpe])
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panic("Failed to remap icu%i memory", vpe);
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}
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/* turn off all irqs by default */
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for_each_possible_cpu(vpe) {
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for (i = 0; i < MAX_IM; i++) {
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/* make sure all irqs are turned off by default */
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ltq_icu_w32(vpe, i, 0, LTQ_ICU_IER);
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/* clear all possibly pending interrupts */
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ltq_icu_w32(vpe, i, ~0, LTQ_ICU_ISR);
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ltq_icu_w32(vpe, i, ~0, LTQ_ICU_IMR);
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/* clear resend */
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ltq_icu_w32(vpe, i, 0, LTQ_ICU_IRSR);
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}
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}
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mips_cpu_irq_init();
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for (i = 0; i < MAX_IM; i++)
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irq_set_chained_handler(i + 2, ltq_hw_irq_handler);
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ltq_domain = irq_domain_add_linear(node,
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(MAX_IM * INT_NUM_IM_OFFSET) + MIPS_CPU_IRQ_CASCADE,
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&irq_domain_ops, 0);
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/* tell oprofile which irq to use */
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ltq_perfcount_irq = irq_create_mapping(ltq_domain, LTQ_PERF_IRQ);
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/* the external interrupts are optional and xway only */
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eiu_node = of_find_compatible_node(NULL, NULL, "lantiq,eiu-xway");
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if (eiu_node && !of_address_to_resource(eiu_node, 0, &res)) {
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/* find out how many external irq sources we have */
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exin_avail = of_property_count_u32_elems(eiu_node,
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"lantiq,eiu-irqs");
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if (exin_avail > MAX_EIU)
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exin_avail = MAX_EIU;
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ret = of_property_read_u32_array(eiu_node, "lantiq,eiu-irqs",
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ltq_eiu_irq, exin_avail);
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if (ret)
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panic("failed to load external irq resources");
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if (!request_mem_region(res.start, resource_size(&res),
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res.name))
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pr_err("Failed to request eiu memory");
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ltq_eiu_membase = ioremap_nocache(res.start,
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resource_size(&res));
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if (!ltq_eiu_membase)
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panic("Failed to remap eiu memory");
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}
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return 0;
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}
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int get_c0_perfcount_int(void)
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{
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return ltq_perfcount_irq;
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}
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EXPORT_SYMBOL_GPL(get_c0_perfcount_int);
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unsigned int get_c0_compare_int(void)
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{
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return CP0_LEGACY_COMPARE_IRQ;
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}
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static const struct of_device_id of_irq_ids[] __initconst = {
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{ .compatible = "lantiq,icu", .data = icu_of_init },
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{},
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};
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void __init arch_init_irq(void)
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{
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of_irq_init(of_irq_ids);
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}
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