mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-27 11:19:37 +00:00
![Linus Torvalds](/assets/img/avatar_default.png)
- move the USB special case that bounced DMA through a device bar into the USB code instead of handling it in the common DMA code (Laurentiu Tudor and Fredrik Noring) - don't dip into the global CMA pool for single page allocations (Nicolin Chen) - fix a crash when allocating memory for the atomic pool failed during boot (Florian Fainelli) - move support for MIPS-style uncached segments to the common code and use that for MIPS and nios2 (me) - make support for DMA_ATTR_NON_CONSISTENT and DMA_ATTR_NO_KERNEL_MAPPING generic (me) - convert nds32 to the generic remapping allocator (me) -----BEGIN PGP SIGNATURE----- iQI/BAABCgApFiEEgdbnc3r/njty3Iq9D55TZVIEUYMFAl0nPqgLHGhjaEBsc3Qu ZGUACgkQD55TZVIEUYNj2hAAxIv2O3wv6V5xhzWwOVo8e/xW1ZLlGAF0/z92u0do 32Tm8jkdAGjZDnyxam7qisMSIjCNykpauQzVVxyUNBRSsn1V5t7KSaH3/OXCOVcr x2VWBirxGO2BbRseaCBjIcA/2qna+VIDGFcNXCtf6rM00YUK6qaJzkMwBKQAeYcM uJMJkaf8qaW4hygLJP8axXiGFdIJyFNLAlJ+ok6kYsJHHJNceOp0bo3CDa2mJBK9 IhraK2zVkyE5EQkQM5cE/Kw1ppPelUKUkHwjgM4wpz2b18WbLu11nKP0hmUcvKRQ heY8xWiKxN0QTgS03ou7EVylyrSAE4dIKgzuA4VO32QCGsWypcAg4iU6s5TX6p9g tZEW2ckE6wbmRdQPyKoDpZg299/eQjRHc4MAA1yinT8tFMokw2tk8Fq1FWyltwL1 8EiP5oNs2qUNvNgqUresl6/f6YOacFi1Q6IhgBVj6d6lyhMhlsHfW4w1XA1siv/I 6l4qJbLohYab6hY7i+mBOd8iG/KrAlr4P6admnv2jDchswbb5t2j+ABE9xv++PFi u1HFqMlxqdWQaXGca2UeCUxUjkwO9N+kHpP+VRz+6D2b64dtCWSu8CN23sYXm2tO ubWIlrQQZPhhMkoFg7XqKSTacd+ut+SXN9Nxsyv548ETV0l1xbiLRHIbhyoIESD5 RAI= =01Fr -----END PGP SIGNATURE----- Merge tag 'dma-mapping-5.3' of git://git.infradead.org/users/hch/dma-mapping Pull dma-mapping updates from Christoph Hellwig: - move the USB special case that bounced DMA through a device bar into the USB code instead of handling it in the common DMA code (Laurentiu Tudor and Fredrik Noring) - don't dip into the global CMA pool for single page allocations (Nicolin Chen) - fix a crash when allocating memory for the atomic pool failed during boot (Florian Fainelli) - move support for MIPS-style uncached segments to the common code and use that for MIPS and nios2 (me) - make support for DMA_ATTR_NON_CONSISTENT and DMA_ATTR_NO_KERNEL_MAPPING generic (me) - convert nds32 to the generic remapping allocator (me) * tag 'dma-mapping-5.3' of git://git.infradead.org/users/hch/dma-mapping: (29 commits) dma-mapping: mark dma_alloc_need_uncached as __always_inline MIPS: only select ARCH_HAS_UNCACHED_SEGMENT for non-coherent platforms usb: host: Fix excessive alignment restriction for local memory allocations lib/genalloc.c: Add algorithm, align and zeroed family of DMA allocators nios2: use the generic uncached segment support in dma-direct nds32: use the generic remapping allocator for coherent DMA allocations arc: use the generic remapping allocator for coherent DMA allocations dma-direct: handle DMA_ATTR_NO_KERNEL_MAPPING in common code dma-direct: handle DMA_ATTR_NON_CONSISTENT in common code dma-mapping: add a dma_alloc_need_uncached helper openrisc: remove the partial DMA_ATTR_NON_CONSISTENT support arc: remove the partial DMA_ATTR_NON_CONSISTENT support arm-nommu: remove the partial DMA_ATTR_NON_CONSISTENT support ARM: dma-mapping: allow larger DMA mask than supported dma-mapping: truncate dma masks to what dma_addr_t can hold iommu/dma: Apply dma_{alloc,free}_contiguous functions dma-remap: Avoid de-referencing NULL atomic_pool MIPS: use the generic uncached segment support in dma-direct dma-direct: provide generic support for uncached kernel segments au1100fb: fix DMA API abuse ...
152 lines
3.9 KiB
C
152 lines
3.9 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
|
|
/*
|
|
* OpenRISC Linux
|
|
*
|
|
* Linux architectural port borrowing liberally from similar works of
|
|
* others. All original copyrights apply as per the original source
|
|
* declaration.
|
|
*
|
|
* Modifications for the OpenRISC architecture:
|
|
* Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com>
|
|
* Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
|
|
*
|
|
* DMA mapping callbacks...
|
|
* As alloc_coherent is the only DMA callback being used currently, that's
|
|
* the only thing implemented properly. The rest need looking into...
|
|
*/
|
|
|
|
#include <linux/dma-noncoherent.h>
|
|
|
|
#include <asm/cpuinfo.h>
|
|
#include <asm/spr_defs.h>
|
|
#include <asm/tlbflush.h>
|
|
|
|
static int
|
|
page_set_nocache(pte_t *pte, unsigned long addr,
|
|
unsigned long next, struct mm_walk *walk)
|
|
{
|
|
unsigned long cl;
|
|
struct cpuinfo_or1k *cpuinfo = &cpuinfo_or1k[smp_processor_id()];
|
|
|
|
pte_val(*pte) |= _PAGE_CI;
|
|
|
|
/*
|
|
* Flush the page out of the TLB so that the new page flags get
|
|
* picked up next time there's an access
|
|
*/
|
|
flush_tlb_page(NULL, addr);
|
|
|
|
/* Flush page out of dcache */
|
|
for (cl = __pa(addr); cl < __pa(next); cl += cpuinfo->dcache_block_size)
|
|
mtspr(SPR_DCBFR, cl);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
page_clear_nocache(pte_t *pte, unsigned long addr,
|
|
unsigned long next, struct mm_walk *walk)
|
|
{
|
|
pte_val(*pte) &= ~_PAGE_CI;
|
|
|
|
/*
|
|
* Flush the page out of the TLB so that the new page flags get
|
|
* picked up next time there's an access
|
|
*/
|
|
flush_tlb_page(NULL, addr);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Alloc "coherent" memory, which for OpenRISC means simply uncached.
|
|
*
|
|
* This function effectively just calls __get_free_pages, sets the
|
|
* cache-inhibit bit on those pages, and makes sure that the pages are
|
|
* flushed out of the cache before they are used.
|
|
*
|
|
* If the NON_CONSISTENT attribute is set, then this function just
|
|
* returns "normal", cachable memory.
|
|
*
|
|
* There are additional flags WEAK_ORDERING and WRITE_COMBINE to take
|
|
* into consideration here, too. All current known implementations of
|
|
* the OR1K support only strongly ordered memory accesses, so that flag
|
|
* is being ignored for now; uncached but write-combined memory is a
|
|
* missing feature of the OR1K.
|
|
*/
|
|
void *
|
|
arch_dma_alloc(struct device *dev, size_t size, dma_addr_t *dma_handle,
|
|
gfp_t gfp, unsigned long attrs)
|
|
{
|
|
unsigned long va;
|
|
void *page;
|
|
struct mm_walk walk = {
|
|
.pte_entry = page_set_nocache,
|
|
.mm = &init_mm
|
|
};
|
|
|
|
page = alloc_pages_exact(size, gfp | __GFP_ZERO);
|
|
if (!page)
|
|
return NULL;
|
|
|
|
/* This gives us the real physical address of the first page. */
|
|
*dma_handle = __pa(page);
|
|
|
|
va = (unsigned long)page;
|
|
|
|
/*
|
|
* We need to iterate through the pages, clearing the dcache for
|
|
* them and setting the cache-inhibit bit.
|
|
*/
|
|
if (walk_page_range(va, va + size, &walk)) {
|
|
free_pages_exact(page, size);
|
|
return NULL;
|
|
}
|
|
|
|
return (void *)va;
|
|
}
|
|
|
|
void
|
|
arch_dma_free(struct device *dev, size_t size, void *vaddr,
|
|
dma_addr_t dma_handle, unsigned long attrs)
|
|
{
|
|
unsigned long va = (unsigned long)vaddr;
|
|
struct mm_walk walk = {
|
|
.pte_entry = page_clear_nocache,
|
|
.mm = &init_mm
|
|
};
|
|
|
|
/* walk_page_range shouldn't be able to fail here */
|
|
WARN_ON(walk_page_range(va, va + size, &walk));
|
|
|
|
free_pages_exact(vaddr, size);
|
|
}
|
|
|
|
void arch_sync_dma_for_device(struct device *dev, phys_addr_t addr, size_t size,
|
|
enum dma_data_direction dir)
|
|
{
|
|
unsigned long cl;
|
|
struct cpuinfo_or1k *cpuinfo = &cpuinfo_or1k[smp_processor_id()];
|
|
|
|
switch (dir) {
|
|
case DMA_TO_DEVICE:
|
|
/* Flush the dcache for the requested range */
|
|
for (cl = addr; cl < addr + size;
|
|
cl += cpuinfo->dcache_block_size)
|
|
mtspr(SPR_DCBFR, cl);
|
|
break;
|
|
case DMA_FROM_DEVICE:
|
|
/* Invalidate the dcache for the requested range */
|
|
for (cl = addr; cl < addr + size;
|
|
cl += cpuinfo->dcache_block_size)
|
|
mtspr(SPR_DCBIR, cl);
|
|
break;
|
|
default:
|
|
/*
|
|
* NOTE: If dir == DMA_BIDIRECTIONAL then there's no need to
|
|
* flush nor invalidate the cache here as the area will need
|
|
* to be manually synced anyway.
|
|
*/
|
|
break;
|
|
}
|
|
}
|