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![Thomas Gleixner](/assets/img/avatar_default.png)
Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details you should have received a copy of the gnu general public license along with this program if not write to the free software foundation inc 675 mass ave cambridge ma 02139 usa extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 441 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Michael Ellerman <mpe@ellerman.id.au> (powerpc) Reviewed-by: Richard Fontana <rfontana@redhat.com> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190520071858.739733335@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
216 lines
4.8 KiB
C
216 lines
4.8 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright 2009-2010, 2012 Freescale Semiconductor, Inc.
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*
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* QorIQ (P1/P2) L2 controller init for Cache-SRAM instantiation
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*
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* Author: Vivek Mahajan <vivek.mahajan@freescale.com>
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of_platform.h>
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#include <asm/io.h>
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#include "fsl_85xx_cache_ctlr.h"
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static char *sram_size;
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static char *sram_offset;
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struct mpc85xx_l2ctlr __iomem *l2ctlr;
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static int get_cache_sram_params(struct sram_parameters *sram_params)
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{
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unsigned long long addr;
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unsigned int size;
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if (!sram_size || (kstrtouint(sram_size, 0, &size) < 0))
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return -EINVAL;
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if (!sram_offset || (kstrtoull(sram_offset, 0, &addr) < 0))
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return -EINVAL;
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sram_params->sram_offset = addr;
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sram_params->sram_size = size;
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return 0;
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}
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static int __init get_size_from_cmdline(char *str)
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{
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if (!str)
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return 0;
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sram_size = str;
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return 1;
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}
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static int __init get_offset_from_cmdline(char *str)
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{
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if (!str)
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return 0;
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sram_offset = str;
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return 1;
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}
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__setup("cache-sram-size=", get_size_from_cmdline);
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__setup("cache-sram-offset=", get_offset_from_cmdline);
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static int mpc85xx_l2ctlr_of_probe(struct platform_device *dev)
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{
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long rval;
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unsigned int rem;
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unsigned char ways;
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const unsigned int *prop;
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unsigned int l2cache_size;
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struct sram_parameters sram_params;
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if (!dev->dev.of_node) {
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dev_err(&dev->dev, "Device's OF-node is NULL\n");
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return -EINVAL;
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}
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prop = of_get_property(dev->dev.of_node, "cache-size", NULL);
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if (!prop) {
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dev_err(&dev->dev, "Missing L2 cache-size\n");
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return -EINVAL;
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}
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l2cache_size = *prop;
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if (get_cache_sram_params(&sram_params))
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return 0; /* fall back to L2 cache only */
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rem = l2cache_size % sram_params.sram_size;
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ways = LOCK_WAYS_FULL * sram_params.sram_size / l2cache_size;
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if (rem || (ways & (ways - 1))) {
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dev_err(&dev->dev, "Illegal cache-sram-size in command line\n");
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return -EINVAL;
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}
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l2ctlr = of_iomap(dev->dev.of_node, 0);
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if (!l2ctlr) {
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dev_err(&dev->dev, "Can't map L2 controller\n");
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return -EINVAL;
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}
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/*
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* Write bits[0-17] to srbar0
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*/
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out_be32(&l2ctlr->srbar0,
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lower_32_bits(sram_params.sram_offset) & L2SRAM_BAR_MSK_LO18);
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/*
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* Write bits[18-21] to srbare0
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*/
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#ifdef CONFIG_PHYS_64BIT
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out_be32(&l2ctlr->srbarea0,
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upper_32_bits(sram_params.sram_offset) & L2SRAM_BARE_MSK_HI4);
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#endif
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clrsetbits_be32(&l2ctlr->ctl, L2CR_L2E, L2CR_L2FI);
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switch (ways) {
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case LOCK_WAYS_EIGHTH:
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setbits32(&l2ctlr->ctl,
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L2CR_L2E | L2CR_L2FI | L2CR_SRAM_EIGHTH);
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break;
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case LOCK_WAYS_TWO_EIGHTH:
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setbits32(&l2ctlr->ctl,
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L2CR_L2E | L2CR_L2FI | L2CR_SRAM_QUART);
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break;
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case LOCK_WAYS_HALF:
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setbits32(&l2ctlr->ctl,
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L2CR_L2E | L2CR_L2FI | L2CR_SRAM_HALF);
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break;
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case LOCK_WAYS_FULL:
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default:
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setbits32(&l2ctlr->ctl,
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L2CR_L2E | L2CR_L2FI | L2CR_SRAM_FULL);
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break;
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}
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eieio();
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rval = instantiate_cache_sram(dev, sram_params);
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if (rval < 0) {
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dev_err(&dev->dev, "Can't instantiate Cache-SRAM\n");
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iounmap(l2ctlr);
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return -EINVAL;
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}
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return 0;
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}
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static int mpc85xx_l2ctlr_of_remove(struct platform_device *dev)
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{
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BUG_ON(!l2ctlr);
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iounmap(l2ctlr);
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remove_cache_sram(dev);
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dev_info(&dev->dev, "MPC85xx L2 controller unloaded\n");
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return 0;
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}
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static const struct of_device_id mpc85xx_l2ctlr_of_match[] = {
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{
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.compatible = "fsl,p2020-l2-cache-controller",
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},
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{
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.compatible = "fsl,p2010-l2-cache-controller",
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},
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{
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.compatible = "fsl,p1020-l2-cache-controller",
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},
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{
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.compatible = "fsl,p1011-l2-cache-controller",
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},
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{
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.compatible = "fsl,p1013-l2-cache-controller",
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},
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{
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.compatible = "fsl,p1022-l2-cache-controller",
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},
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{
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.compatible = "fsl,mpc8548-l2-cache-controller",
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},
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{ .compatible = "fsl,mpc8544-l2-cache-controller",},
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{ .compatible = "fsl,mpc8572-l2-cache-controller",},
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{ .compatible = "fsl,mpc8536-l2-cache-controller",},
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{ .compatible = "fsl,p1021-l2-cache-controller",},
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{ .compatible = "fsl,p1012-l2-cache-controller",},
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{ .compatible = "fsl,p1025-l2-cache-controller",},
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{ .compatible = "fsl,p1016-l2-cache-controller",},
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{ .compatible = "fsl,p1024-l2-cache-controller",},
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{ .compatible = "fsl,p1015-l2-cache-controller",},
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{ .compatible = "fsl,p1010-l2-cache-controller",},
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{ .compatible = "fsl,bsc9131-l2-cache-controller",},
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{},
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};
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static struct platform_driver mpc85xx_l2ctlr_of_platform_driver = {
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.driver = {
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.name = "fsl-l2ctlr",
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.of_match_table = mpc85xx_l2ctlr_of_match,
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},
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.probe = mpc85xx_l2ctlr_of_probe,
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.remove = mpc85xx_l2ctlr_of_remove,
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};
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static __init int mpc85xx_l2ctlr_of_init(void)
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{
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return platform_driver_register(&mpc85xx_l2ctlr_of_platform_driver);
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}
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static void __exit mpc85xx_l2ctlr_of_exit(void)
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{
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platform_driver_unregister(&mpc85xx_l2ctlr_of_platform_driver);
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}
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subsys_initcall(mpc85xx_l2ctlr_of_init);
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module_exit(mpc85xx_l2ctlr_of_exit);
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MODULE_DESCRIPTION("Freescale MPC85xx L2 controller init");
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MODULE_LICENSE("GPL v2");
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