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![Hauke Mehrtens](/assets/img/avatar_default.png)
The ltq_r32() and ltq_w32() macros use the __raw_readl() and
__raw_writel() functions which do not swap the value to little endian.
On the big endian vrx200 SoC the UART is operated in big endian IO mode,
the readl() and write() functions convert the value to little endian
first and then the driver does not work any more on this SoC.
Currently the vrx200 SoC selects the CONFIG_SWAP_IO_SPACE option,
without this option the serial driver would work, but PCI devices do not
work any more.
This patch makes the driver use the __raw_readl() and __raw_writel()
functions which do not swap the endianness. On big endian system it is
assumed that the device should be access in big endian IO mode and on a
little endian system it would be access in little endian mode.
Fixes: 89b8bd2082
("serial: lantiq: Use readl/writel instead of ltq_r32/ltq_w32")
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Acked-by: John Crispin <john@phrozen.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
804 lines
19 KiB
C
804 lines
19 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
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*
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* Copyright (C) 2004 Infineon IFAP DC COM CPE
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* Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
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* Copyright (C) 2007 John Crispin <john@phrozen.org>
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* Copyright (C) 2010 Thomas Langer, <thomas.langer@lantiq.com>
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*/
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#include <linux/clk.h>
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#include <linux/console.h>
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#include <linux/device.h>
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#include <linux/gpio.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/ioport.h>
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#include <linux/lantiq.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/of_platform.h>
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#include <linux/serial.h>
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#include <linux/serial_core.h>
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#include <linux/slab.h>
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#include <linux/sysrq.h>
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#include <linux/tty.h>
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#include <linux/tty_flip.h>
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#define PORT_LTQ_ASC 111
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#define MAXPORTS 2
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#define UART_DUMMY_UER_RX 1
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#define DRVNAME "lantiq,asc"
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#ifdef __BIG_ENDIAN
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#define LTQ_ASC_TBUF (0x0020 + 3)
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#define LTQ_ASC_RBUF (0x0024 + 3)
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#else
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#define LTQ_ASC_TBUF 0x0020
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#define LTQ_ASC_RBUF 0x0024
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#endif
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#define LTQ_ASC_FSTAT 0x0048
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#define LTQ_ASC_WHBSTATE 0x0018
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#define LTQ_ASC_STATE 0x0014
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#define LTQ_ASC_IRNCR 0x00F8
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#define LTQ_ASC_CLC 0x0000
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#define LTQ_ASC_ID 0x0008
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#define LTQ_ASC_PISEL 0x0004
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#define LTQ_ASC_TXFCON 0x0044
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#define LTQ_ASC_RXFCON 0x0040
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#define LTQ_ASC_CON 0x0010
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#define LTQ_ASC_BG 0x0050
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#define LTQ_ASC_IRNREN 0x00F4
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#define ASC_IRNREN_TX 0x1
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#define ASC_IRNREN_RX 0x2
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#define ASC_IRNREN_ERR 0x4
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#define ASC_IRNREN_TX_BUF 0x8
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#define ASC_IRNCR_TIR 0x1
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#define ASC_IRNCR_RIR 0x2
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#define ASC_IRNCR_EIR 0x4
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#define ASCOPT_CSIZE 0x3
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#define TXFIFO_FL 1
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#define RXFIFO_FL 1
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#define ASCCLC_DISS 0x2
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#define ASCCLC_RMCMASK 0x0000FF00
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#define ASCCLC_RMCOFFSET 8
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#define ASCCON_M_8ASYNC 0x0
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#define ASCCON_M_7ASYNC 0x2
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#define ASCCON_ODD 0x00000020
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#define ASCCON_STP 0x00000080
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#define ASCCON_BRS 0x00000100
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#define ASCCON_FDE 0x00000200
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#define ASCCON_R 0x00008000
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#define ASCCON_FEN 0x00020000
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#define ASCCON_ROEN 0x00080000
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#define ASCCON_TOEN 0x00100000
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#define ASCSTATE_PE 0x00010000
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#define ASCSTATE_FE 0x00020000
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#define ASCSTATE_ROE 0x00080000
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#define ASCSTATE_ANY (ASCSTATE_ROE|ASCSTATE_PE|ASCSTATE_FE)
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#define ASCWHBSTATE_CLRREN 0x00000001
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#define ASCWHBSTATE_SETREN 0x00000002
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#define ASCWHBSTATE_CLRPE 0x00000004
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#define ASCWHBSTATE_CLRFE 0x00000008
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#define ASCWHBSTATE_CLRROE 0x00000020
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#define ASCTXFCON_TXFEN 0x0001
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#define ASCTXFCON_TXFFLU 0x0002
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#define ASCTXFCON_TXFITLMASK 0x3F00
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#define ASCTXFCON_TXFITLOFF 8
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#define ASCRXFCON_RXFEN 0x0001
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#define ASCRXFCON_RXFFLU 0x0002
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#define ASCRXFCON_RXFITLMASK 0x3F00
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#define ASCRXFCON_RXFITLOFF 8
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#define ASCFSTAT_RXFFLMASK 0x003F
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#define ASCFSTAT_TXFFLMASK 0x3F00
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#define ASCFSTAT_TXFREEMASK 0x3F000000
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#define ASCFSTAT_TXFREEOFF 24
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static void lqasc_tx_chars(struct uart_port *port);
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static struct ltq_uart_port *lqasc_port[MAXPORTS];
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static struct uart_driver lqasc_reg;
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static DEFINE_SPINLOCK(ltq_asc_lock);
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struct ltq_uart_port {
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struct uart_port port;
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/* clock used to derive divider */
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struct clk *freqclk;
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/* clock gating of the ASC core */
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struct clk *clk;
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unsigned int tx_irq;
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unsigned int rx_irq;
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unsigned int err_irq;
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};
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static inline void asc_update_bits(u32 clear, u32 set, void __iomem *reg)
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{
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u32 tmp = __raw_readl(reg);
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__raw_writel((tmp & ~clear) | set, reg);
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}
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static inline struct
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ltq_uart_port *to_ltq_uart_port(struct uart_port *port)
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{
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return container_of(port, struct ltq_uart_port, port);
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}
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static void
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lqasc_stop_tx(struct uart_port *port)
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{
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return;
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}
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static void
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lqasc_start_tx(struct uart_port *port)
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{
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unsigned long flags;
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spin_lock_irqsave(<q_asc_lock, flags);
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lqasc_tx_chars(port);
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spin_unlock_irqrestore(<q_asc_lock, flags);
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return;
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}
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static void
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lqasc_stop_rx(struct uart_port *port)
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{
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__raw_writel(ASCWHBSTATE_CLRREN, port->membase + LTQ_ASC_WHBSTATE);
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}
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static int
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lqasc_rx_chars(struct uart_port *port)
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{
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struct tty_port *tport = &port->state->port;
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unsigned int ch = 0, rsr = 0, fifocnt;
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fifocnt = __raw_readl(port->membase + LTQ_ASC_FSTAT) &
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ASCFSTAT_RXFFLMASK;
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while (fifocnt--) {
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u8 flag = TTY_NORMAL;
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ch = readb(port->membase + LTQ_ASC_RBUF);
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rsr = (__raw_readl(port->membase + LTQ_ASC_STATE)
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& ASCSTATE_ANY) | UART_DUMMY_UER_RX;
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tty_flip_buffer_push(tport);
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port->icount.rx++;
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/*
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* Note that the error handling code is
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* out of the main execution path
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*/
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if (rsr & ASCSTATE_ANY) {
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if (rsr & ASCSTATE_PE) {
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port->icount.parity++;
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asc_update_bits(0, ASCWHBSTATE_CLRPE,
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port->membase + LTQ_ASC_WHBSTATE);
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} else if (rsr & ASCSTATE_FE) {
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port->icount.frame++;
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asc_update_bits(0, ASCWHBSTATE_CLRFE,
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port->membase + LTQ_ASC_WHBSTATE);
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}
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if (rsr & ASCSTATE_ROE) {
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port->icount.overrun++;
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asc_update_bits(0, ASCWHBSTATE_CLRROE,
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port->membase + LTQ_ASC_WHBSTATE);
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}
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rsr &= port->read_status_mask;
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if (rsr & ASCSTATE_PE)
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flag = TTY_PARITY;
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else if (rsr & ASCSTATE_FE)
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flag = TTY_FRAME;
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}
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if ((rsr & port->ignore_status_mask) == 0)
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tty_insert_flip_char(tport, ch, flag);
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if (rsr & ASCSTATE_ROE)
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/*
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* Overrun is special, since it's reported
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* immediately, and doesn't affect the current
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* character
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*/
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tty_insert_flip_char(tport, 0, TTY_OVERRUN);
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}
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if (ch != 0)
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tty_flip_buffer_push(tport);
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return 0;
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}
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static void
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lqasc_tx_chars(struct uart_port *port)
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{
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struct circ_buf *xmit = &port->state->xmit;
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if (uart_tx_stopped(port)) {
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lqasc_stop_tx(port);
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return;
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}
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while (((__raw_readl(port->membase + LTQ_ASC_FSTAT) &
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ASCFSTAT_TXFREEMASK) >> ASCFSTAT_TXFREEOFF) != 0) {
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if (port->x_char) {
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writeb(port->x_char, port->membase + LTQ_ASC_TBUF);
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port->icount.tx++;
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port->x_char = 0;
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continue;
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}
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if (uart_circ_empty(xmit))
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break;
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writeb(port->state->xmit.buf[port->state->xmit.tail],
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port->membase + LTQ_ASC_TBUF);
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xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
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port->icount.tx++;
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}
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if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
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uart_write_wakeup(port);
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}
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static irqreturn_t
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lqasc_tx_int(int irq, void *_port)
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{
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unsigned long flags;
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struct uart_port *port = (struct uart_port *)_port;
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spin_lock_irqsave(<q_asc_lock, flags);
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__raw_writel(ASC_IRNCR_TIR, port->membase + LTQ_ASC_IRNCR);
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spin_unlock_irqrestore(<q_asc_lock, flags);
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lqasc_start_tx(port);
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return IRQ_HANDLED;
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}
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static irqreturn_t
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lqasc_err_int(int irq, void *_port)
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{
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unsigned long flags;
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struct uart_port *port = (struct uart_port *)_port;
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spin_lock_irqsave(<q_asc_lock, flags);
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/* clear any pending interrupts */
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asc_update_bits(0, ASCWHBSTATE_CLRPE | ASCWHBSTATE_CLRFE |
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ASCWHBSTATE_CLRROE, port->membase + LTQ_ASC_WHBSTATE);
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spin_unlock_irqrestore(<q_asc_lock, flags);
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return IRQ_HANDLED;
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}
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static irqreturn_t
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lqasc_rx_int(int irq, void *_port)
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{
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unsigned long flags;
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struct uart_port *port = (struct uart_port *)_port;
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spin_lock_irqsave(<q_asc_lock, flags);
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__raw_writel(ASC_IRNCR_RIR, port->membase + LTQ_ASC_IRNCR);
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lqasc_rx_chars(port);
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spin_unlock_irqrestore(<q_asc_lock, flags);
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return IRQ_HANDLED;
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}
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static unsigned int
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lqasc_tx_empty(struct uart_port *port)
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{
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int status;
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status = __raw_readl(port->membase + LTQ_ASC_FSTAT) &
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ASCFSTAT_TXFFLMASK;
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return status ? 0 : TIOCSER_TEMT;
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}
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static unsigned int
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lqasc_get_mctrl(struct uart_port *port)
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{
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return TIOCM_CTS | TIOCM_CAR | TIOCM_DSR;
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}
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static void
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lqasc_set_mctrl(struct uart_port *port, u_int mctrl)
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{
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}
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static void
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lqasc_break_ctl(struct uart_port *port, int break_state)
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{
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}
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static int
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lqasc_startup(struct uart_port *port)
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{
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struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
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int retval;
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if (!IS_ERR(ltq_port->clk))
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clk_prepare_enable(ltq_port->clk);
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port->uartclk = clk_get_rate(ltq_port->freqclk);
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asc_update_bits(ASCCLC_DISS | ASCCLC_RMCMASK, (1 << ASCCLC_RMCOFFSET),
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port->membase + LTQ_ASC_CLC);
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__raw_writel(0, port->membase + LTQ_ASC_PISEL);
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__raw_writel(
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((TXFIFO_FL << ASCTXFCON_TXFITLOFF) & ASCTXFCON_TXFITLMASK) |
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ASCTXFCON_TXFEN | ASCTXFCON_TXFFLU,
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port->membase + LTQ_ASC_TXFCON);
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__raw_writel(
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((RXFIFO_FL << ASCRXFCON_RXFITLOFF) & ASCRXFCON_RXFITLMASK)
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| ASCRXFCON_RXFEN | ASCRXFCON_RXFFLU,
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port->membase + LTQ_ASC_RXFCON);
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/* make sure other settings are written to hardware before
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* setting enable bits
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*/
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wmb();
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asc_update_bits(0, ASCCON_M_8ASYNC | ASCCON_FEN | ASCCON_TOEN |
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ASCCON_ROEN, port->membase + LTQ_ASC_CON);
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retval = request_irq(ltq_port->tx_irq, lqasc_tx_int,
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0, "asc_tx", port);
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if (retval) {
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pr_err("failed to request lqasc_tx_int\n");
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return retval;
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}
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retval = request_irq(ltq_port->rx_irq, lqasc_rx_int,
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0, "asc_rx", port);
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if (retval) {
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pr_err("failed to request lqasc_rx_int\n");
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goto err1;
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}
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retval = request_irq(ltq_port->err_irq, lqasc_err_int,
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0, "asc_err", port);
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if (retval) {
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pr_err("failed to request lqasc_err_int\n");
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goto err2;
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}
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__raw_writel(ASC_IRNREN_RX | ASC_IRNREN_ERR | ASC_IRNREN_TX,
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port->membase + LTQ_ASC_IRNREN);
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return 0;
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err2:
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free_irq(ltq_port->rx_irq, port);
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err1:
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free_irq(ltq_port->tx_irq, port);
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return retval;
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}
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static void
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lqasc_shutdown(struct uart_port *port)
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{
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struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
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free_irq(ltq_port->tx_irq, port);
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free_irq(ltq_port->rx_irq, port);
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free_irq(ltq_port->err_irq, port);
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__raw_writel(0, port->membase + LTQ_ASC_CON);
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asc_update_bits(ASCRXFCON_RXFEN, ASCRXFCON_RXFFLU,
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port->membase + LTQ_ASC_RXFCON);
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asc_update_bits(ASCTXFCON_TXFEN, ASCTXFCON_TXFFLU,
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port->membase + LTQ_ASC_TXFCON);
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if (!IS_ERR(ltq_port->clk))
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clk_disable_unprepare(ltq_port->clk);
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}
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static void
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lqasc_set_termios(struct uart_port *port,
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struct ktermios *new, struct ktermios *old)
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{
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unsigned int cflag;
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unsigned int iflag;
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unsigned int divisor;
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unsigned int baud;
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unsigned int con = 0;
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unsigned long flags;
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cflag = new->c_cflag;
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iflag = new->c_iflag;
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switch (cflag & CSIZE) {
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case CS7:
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con = ASCCON_M_7ASYNC;
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break;
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case CS5:
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case CS6:
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default:
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new->c_cflag &= ~ CSIZE;
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new->c_cflag |= CS8;
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con = ASCCON_M_8ASYNC;
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break;
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}
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cflag &= ~CMSPAR; /* Mark/Space parity is not supported */
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if (cflag & CSTOPB)
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con |= ASCCON_STP;
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if (cflag & PARENB) {
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if (!(cflag & PARODD))
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con &= ~ASCCON_ODD;
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else
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con |= ASCCON_ODD;
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}
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port->read_status_mask = ASCSTATE_ROE;
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if (iflag & INPCK)
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port->read_status_mask |= ASCSTATE_FE | ASCSTATE_PE;
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port->ignore_status_mask = 0;
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if (iflag & IGNPAR)
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port->ignore_status_mask |= ASCSTATE_FE | ASCSTATE_PE;
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if (iflag & IGNBRK) {
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/*
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* If we're ignoring parity and break indicators,
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* ignore overruns too (for real raw support).
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*/
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if (iflag & IGNPAR)
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port->ignore_status_mask |= ASCSTATE_ROE;
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}
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if ((cflag & CREAD) == 0)
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port->ignore_status_mask |= UART_DUMMY_UER_RX;
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/* set error signals - framing, parity and overrun, enable receiver */
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con |= ASCCON_FEN | ASCCON_TOEN | ASCCON_ROEN;
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spin_lock_irqsave(<q_asc_lock, flags);
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/* set up CON */
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asc_update_bits(0, con, port->membase + LTQ_ASC_CON);
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/* Set baud rate - take a divider of 2 into account */
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baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16);
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divisor = uart_get_divisor(port, baud);
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divisor = divisor / 2 - 1;
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/* disable the baudrate generator */
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asc_update_bits(ASCCON_R, 0, port->membase + LTQ_ASC_CON);
|
|
|
|
/* make sure the fractional divider is off */
|
|
asc_update_bits(ASCCON_FDE, 0, port->membase + LTQ_ASC_CON);
|
|
|
|
/* set up to use divisor of 2 */
|
|
asc_update_bits(ASCCON_BRS, 0, port->membase + LTQ_ASC_CON);
|
|
|
|
/* now we can write the new baudrate into the register */
|
|
__raw_writel(divisor, port->membase + LTQ_ASC_BG);
|
|
|
|
/* turn the baudrate generator back on */
|
|
asc_update_bits(0, ASCCON_R, port->membase + LTQ_ASC_CON);
|
|
|
|
/* enable rx */
|
|
__raw_writel(ASCWHBSTATE_SETREN, port->membase + LTQ_ASC_WHBSTATE);
|
|
|
|
spin_unlock_irqrestore(<q_asc_lock, flags);
|
|
|
|
/* Don't rewrite B0 */
|
|
if (tty_termios_baud_rate(new))
|
|
tty_termios_encode_baud_rate(new, baud, baud);
|
|
|
|
uart_update_timeout(port, cflag, baud);
|
|
}
|
|
|
|
static const char*
|
|
lqasc_type(struct uart_port *port)
|
|
{
|
|
if (port->type == PORT_LTQ_ASC)
|
|
return DRVNAME;
|
|
else
|
|
return NULL;
|
|
}
|
|
|
|
static void
|
|
lqasc_release_port(struct uart_port *port)
|
|
{
|
|
struct platform_device *pdev = to_platform_device(port->dev);
|
|
|
|
if (port->flags & UPF_IOREMAP) {
|
|
devm_iounmap(&pdev->dev, port->membase);
|
|
port->membase = NULL;
|
|
}
|
|
}
|
|
|
|
static int
|
|
lqasc_request_port(struct uart_port *port)
|
|
{
|
|
struct platform_device *pdev = to_platform_device(port->dev);
|
|
struct resource *res;
|
|
int size;
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
if (!res) {
|
|
dev_err(&pdev->dev, "cannot obtain I/O memory region");
|
|
return -ENODEV;
|
|
}
|
|
size = resource_size(res);
|
|
|
|
res = devm_request_mem_region(&pdev->dev, res->start,
|
|
size, dev_name(&pdev->dev));
|
|
if (!res) {
|
|
dev_err(&pdev->dev, "cannot request I/O memory region");
|
|
return -EBUSY;
|
|
}
|
|
|
|
if (port->flags & UPF_IOREMAP) {
|
|
port->membase = devm_ioremap_nocache(&pdev->dev,
|
|
port->mapbase, size);
|
|
if (port->membase == NULL)
|
|
return -ENOMEM;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static void
|
|
lqasc_config_port(struct uart_port *port, int flags)
|
|
{
|
|
if (flags & UART_CONFIG_TYPE) {
|
|
port->type = PORT_LTQ_ASC;
|
|
lqasc_request_port(port);
|
|
}
|
|
}
|
|
|
|
static int
|
|
lqasc_verify_port(struct uart_port *port,
|
|
struct serial_struct *ser)
|
|
{
|
|
int ret = 0;
|
|
if (ser->type != PORT_UNKNOWN && ser->type != PORT_LTQ_ASC)
|
|
ret = -EINVAL;
|
|
if (ser->irq < 0 || ser->irq >= NR_IRQS)
|
|
ret = -EINVAL;
|
|
if (ser->baud_base < 9600)
|
|
ret = -EINVAL;
|
|
return ret;
|
|
}
|
|
|
|
static const struct uart_ops lqasc_pops = {
|
|
.tx_empty = lqasc_tx_empty,
|
|
.set_mctrl = lqasc_set_mctrl,
|
|
.get_mctrl = lqasc_get_mctrl,
|
|
.stop_tx = lqasc_stop_tx,
|
|
.start_tx = lqasc_start_tx,
|
|
.stop_rx = lqasc_stop_rx,
|
|
.break_ctl = lqasc_break_ctl,
|
|
.startup = lqasc_startup,
|
|
.shutdown = lqasc_shutdown,
|
|
.set_termios = lqasc_set_termios,
|
|
.type = lqasc_type,
|
|
.release_port = lqasc_release_port,
|
|
.request_port = lqasc_request_port,
|
|
.config_port = lqasc_config_port,
|
|
.verify_port = lqasc_verify_port,
|
|
};
|
|
|
|
static void
|
|
lqasc_console_putchar(struct uart_port *port, int ch)
|
|
{
|
|
int fifofree;
|
|
|
|
if (!port->membase)
|
|
return;
|
|
|
|
do {
|
|
fifofree = (__raw_readl(port->membase + LTQ_ASC_FSTAT)
|
|
& ASCFSTAT_TXFREEMASK) >> ASCFSTAT_TXFREEOFF;
|
|
} while (fifofree == 0);
|
|
writeb(ch, port->membase + LTQ_ASC_TBUF);
|
|
}
|
|
|
|
static void lqasc_serial_port_write(struct uart_port *port, const char *s,
|
|
u_int count)
|
|
{
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(<q_asc_lock, flags);
|
|
uart_console_write(port, s, count, lqasc_console_putchar);
|
|
spin_unlock_irqrestore(<q_asc_lock, flags);
|
|
}
|
|
|
|
static void
|
|
lqasc_console_write(struct console *co, const char *s, u_int count)
|
|
{
|
|
struct ltq_uart_port *ltq_port;
|
|
|
|
if (co->index >= MAXPORTS)
|
|
return;
|
|
|
|
ltq_port = lqasc_port[co->index];
|
|
if (!ltq_port)
|
|
return;
|
|
|
|
lqasc_serial_port_write(<q_port->port, s, count);
|
|
}
|
|
|
|
static int __init
|
|
lqasc_console_setup(struct console *co, char *options)
|
|
{
|
|
struct ltq_uart_port *ltq_port;
|
|
struct uart_port *port;
|
|
int baud = 115200;
|
|
int bits = 8;
|
|
int parity = 'n';
|
|
int flow = 'n';
|
|
|
|
if (co->index >= MAXPORTS)
|
|
return -ENODEV;
|
|
|
|
ltq_port = lqasc_port[co->index];
|
|
if (!ltq_port)
|
|
return -ENODEV;
|
|
|
|
port = <q_port->port;
|
|
|
|
if (!IS_ERR(ltq_port->clk))
|
|
clk_prepare_enable(ltq_port->clk);
|
|
|
|
port->uartclk = clk_get_rate(ltq_port->freqclk);
|
|
|
|
if (options)
|
|
uart_parse_options(options, &baud, &parity, &bits, &flow);
|
|
return uart_set_options(port, co, baud, parity, bits, flow);
|
|
}
|
|
|
|
static struct console lqasc_console = {
|
|
.name = "ttyLTQ",
|
|
.write = lqasc_console_write,
|
|
.device = uart_console_device,
|
|
.setup = lqasc_console_setup,
|
|
.flags = CON_PRINTBUFFER,
|
|
.index = -1,
|
|
.data = &lqasc_reg,
|
|
};
|
|
|
|
static int __init
|
|
lqasc_console_init(void)
|
|
{
|
|
register_console(&lqasc_console);
|
|
return 0;
|
|
}
|
|
console_initcall(lqasc_console_init);
|
|
|
|
static void lqasc_serial_early_console_write(struct console *co,
|
|
const char *s,
|
|
u_int count)
|
|
{
|
|
struct earlycon_device *dev = co->data;
|
|
|
|
lqasc_serial_port_write(&dev->port, s, count);
|
|
}
|
|
|
|
static int __init
|
|
lqasc_serial_early_console_setup(struct earlycon_device *device,
|
|
const char *opt)
|
|
{
|
|
if (!device->port.membase)
|
|
return -ENODEV;
|
|
|
|
device->con->write = lqasc_serial_early_console_write;
|
|
return 0;
|
|
}
|
|
OF_EARLYCON_DECLARE(lantiq, DRVNAME, lqasc_serial_early_console_setup);
|
|
|
|
static struct uart_driver lqasc_reg = {
|
|
.owner = THIS_MODULE,
|
|
.driver_name = DRVNAME,
|
|
.dev_name = "ttyLTQ",
|
|
.major = 0,
|
|
.minor = 0,
|
|
.nr = MAXPORTS,
|
|
.cons = &lqasc_console,
|
|
};
|
|
|
|
static int __init
|
|
lqasc_probe(struct platform_device *pdev)
|
|
{
|
|
struct device_node *node = pdev->dev.of_node;
|
|
struct ltq_uart_port *ltq_port;
|
|
struct uart_port *port;
|
|
struct resource *mmres, irqres[3];
|
|
int line;
|
|
int ret;
|
|
|
|
mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
ret = of_irq_to_resource_table(node, irqres, 3);
|
|
if (!mmres || (ret != 3)) {
|
|
dev_err(&pdev->dev,
|
|
"failed to get memory/irq for serial port\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
/* get serial id */
|
|
line = of_alias_get_id(node, "serial");
|
|
if (line < 0) {
|
|
if (IS_ENABLED(CONFIG_LANTIQ)) {
|
|
if (mmres->start == CPHYSADDR(LTQ_EARLY_ASC))
|
|
line = 0;
|
|
else
|
|
line = 1;
|
|
} else {
|
|
dev_err(&pdev->dev, "failed to get alias id, errno %d\n",
|
|
line);
|
|
return line;
|
|
}
|
|
}
|
|
|
|
if (lqasc_port[line]) {
|
|
dev_err(&pdev->dev, "port %d already allocated\n", line);
|
|
return -EBUSY;
|
|
}
|
|
|
|
ltq_port = devm_kzalloc(&pdev->dev, sizeof(struct ltq_uart_port),
|
|
GFP_KERNEL);
|
|
if (!ltq_port)
|
|
return -ENOMEM;
|
|
|
|
port = <q_port->port;
|
|
|
|
port->iotype = SERIAL_IO_MEM;
|
|
port->flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP;
|
|
port->ops = &lqasc_pops;
|
|
port->fifosize = 16;
|
|
port->type = PORT_LTQ_ASC,
|
|
port->line = line;
|
|
port->dev = &pdev->dev;
|
|
/* unused, just to be backward-compatible */
|
|
port->irq = irqres[0].start;
|
|
port->mapbase = mmres->start;
|
|
|
|
if (IS_ENABLED(CONFIG_LANTIQ) && !IS_ENABLED(CONFIG_COMMON_CLK))
|
|
ltq_port->freqclk = clk_get_fpi();
|
|
else
|
|
ltq_port->freqclk = devm_clk_get(&pdev->dev, "freq");
|
|
|
|
|
|
if (IS_ERR(ltq_port->freqclk)) {
|
|
pr_err("failed to get fpi clk\n");
|
|
return -ENOENT;
|
|
}
|
|
|
|
/* not all asc ports have clock gates, lets ignore the return code */
|
|
if (IS_ENABLED(CONFIG_LANTIQ) && !IS_ENABLED(CONFIG_COMMON_CLK))
|
|
ltq_port->clk = clk_get(&pdev->dev, NULL);
|
|
else
|
|
ltq_port->clk = devm_clk_get(&pdev->dev, "asc");
|
|
|
|
ltq_port->tx_irq = irqres[0].start;
|
|
ltq_port->rx_irq = irqres[1].start;
|
|
ltq_port->err_irq = irqres[2].start;
|
|
|
|
lqasc_port[line] = ltq_port;
|
|
platform_set_drvdata(pdev, ltq_port);
|
|
|
|
ret = uart_add_one_port(&lqasc_reg, port);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static const struct of_device_id ltq_asc_match[] = {
|
|
{ .compatible = DRVNAME },
|
|
{},
|
|
};
|
|
|
|
static struct platform_driver lqasc_driver = {
|
|
.driver = {
|
|
.name = DRVNAME,
|
|
.of_match_table = ltq_asc_match,
|
|
},
|
|
};
|
|
|
|
static int __init
|
|
init_lqasc(void)
|
|
{
|
|
int ret;
|
|
|
|
ret = uart_register_driver(&lqasc_reg);
|
|
if (ret != 0)
|
|
return ret;
|
|
|
|
ret = platform_driver_probe(&lqasc_driver, lqasc_probe);
|
|
if (ret != 0)
|
|
uart_unregister_driver(&lqasc_reg);
|
|
|
|
return ret;
|
|
}
|
|
device_initcall(init_lqasc);
|