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cycle: Core changes: - Device links can optionally be added between a pin control producer and its consumers. This will affect how the system power management is handled: a pin controller will not suspend before all of its consumers have been suspended. This was necessary for the ST Microelectronics STMFX expander and need to be tested on other systems as well: it makes sense to make this default in the long run. Right now it is opt-in per driver. - Drive strength can be specified in microamps. With decreases in silicon technology, milliamps isn't granular enough, let's make it possible to select drive strengths in microamps. Right now the Meson (AMlogic) driver needs this. New drivers: - New subdriver for the Tegra 194 SoC. - New subdriver for the Qualcomm SDM845. - New subdriver for the Qualcomm SM8150. - New subdriver for the Freescale i.MX8MN (Freescale is now a product line of NXP). - New subdriver for Marvell MV98DX1135. Driver improvements: - The Bitmain BM1880 driver now supports pin config in addition to muxing. - The Qualcomm drivers can now reserve some GPIOs as taken aside and not usable for users. This is used in ACPI systems to take out some GPIO lines used by the BIOS so that noone else (neither kernel nor userspace) will play with them by mistake and crash the machine. - A slew of refurbishing around the Aspeed drivers (board management controllers for servers) in preparation for the new Aspeed AST2600 SoC. - A slew of improvements over the SH PFC drivers as usual. - Misc cleanups and fixes. -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEElDRnuGcz/wPCXQWMQRCzN7AZXXMFAl0oTPcACgkQQRCzN7AZ XXNTsw//aNPfkJS8gRszv58G56lyuO8h6Cq4m5eDpzhlpjx5qjELgi9h2UNGINqD 7CWxo35ufbKe0fDIcqpXmtuDMtSu6MuKT3SMepuw9uf9wxyndK4RIuyb0lpAJrx2 +NMPxzS+ARlrMmcfvXPRyPWHqAkXsQk6zcCgiuNCPtROkOZgs1YZ3+pemZw2/FMq gSLTO/95p0TPWr6YAlpByqfsA1A/onEm9HOiU2INV7DrAfUj7mnkuC1nZ4IJDFcv Gn6qQVQPah+MBzkwt4WXy5kDRozCIbg7x+FQBw3KAO23TrLDTFuNsYIWGFcP2CN2 eT8iSP3cWrXNUuEgcPD59aO07rhFooT+QBQFt2ih1dJCV1u/795wb57nxSh1YDcO M2tG+AW2EZky65FXwhLW2rq3LvmTM4kiEz3mA/DrcOAKvvQllK+6FKEhNy0StstP yvvlqoXdgH3sfOnWTAyHr35qA/pMuGEXSryWTJPqpflCvZ3wxNk+IV5nyPAtfaFz CK7U0Ya7NaEp/5ZlpE720apJ4uSqmRrLwk5Y1eKQvT46mGOk3rC9ZPIMXc8mB10/ mJ9mTubi1t4uIPnBl/T1T7f8QhNtr9hOY6wjLf1LoMeJ1XVNBqA+2uydOlBJ1iop RQ7y/Jl1SZ/gBzKCmvjPHT2+0Oui9oXGd9bQi0xQKO5Lus/nAIg= =Wdw1 -----END PGP SIGNATURE----- Merge tag 'pinctrl-v5.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "This is the bulk of pin control changes for the v5.3 kernel cycle: Core changes: - Device links can optionally be added between a pin control producer and its consumers. This will affect how the system power management is handled: a pin controller will not suspend before all of its consumers have been suspended. This was necessary for the ST Microelectronics STMFX expander and need to be tested on other systems as well: it makes sense to make this default in the long run. Right now it is opt-in per driver. - Drive strength can be specified in microamps. With decreases in silicon technology, milliamps isn't granular enough, let's make it possible to select drive strengths in microamps. Right now the Meson (AMlogic) driver needs this. New drivers: - New subdriver for the Tegra 194 SoC. - New subdriver for the Qualcomm SDM845. - New subdriver for the Qualcomm SM8150. - New subdriver for the Freescale i.MX8MN (Freescale is now a product line of NXP). - New subdriver for Marvell MV98DX1135. Driver improvements: - The Bitmain BM1880 driver now supports pin config in addition to muxing. - The Qualcomm drivers can now reserve some GPIOs as taken aside and not usable for users. This is used in ACPI systems to take out some GPIO lines used by the BIOS so that noone else (neither kernel nor userspace) will play with them by mistake and crash the machine. - A slew of refurbishing around the Aspeed drivers (board management controllers for servers) in preparation for the new Aspeed AST2600 SoC. - A slew of improvements over the SH PFC drivers as usual. - Misc cleanups and fixes" * tag 'pinctrl-v5.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (106 commits) pinctrl: aspeed: Strip moved macros and structs from private header pinctrl: aspeed: Fix missed include pinctrl: baytrail: Use GENMASK() consistently pinctrl: baytrail: Re-use data structures from pinctrl-intel.h pinctrl: baytrail: Use defined macro instead of magic in byt_get_gpio_mux() pinctrl: qcom: Add SM8150 pinctrl driver dt-bindings: pinctrl: qcom: Add SM8150 pinctrl binding dt-bindings: pinctrl: qcom: Document missing gpio nodes pinctrl: aspeed: Add implementation-related documentation pinctrl: aspeed: Split out pinmux from general pinctrl pinctrl: aspeed: Clarify comment about strapping W1C pinctrl: aspeed: Correct comment that is no longer true MAINTAINERS: Add entry for ASPEED pinctrl drivers dt-bindings: pinctrl: aspeed: Convert AST2500 bindings to json-schema dt-bindings: pinctrl: aspeed: Convert AST2400 bindings to json-schema dt-bindings: pinctrl: aspeed: Split bindings document in two pinctrl: qcom: Add irq_enable callback for msm gpio pinctrl: madera: Fixup SPDX headers pinctrl: qcom: sdm845: Fix CONFIG preprocessor guard pinctrl: tegra: Add bitmask support for parked bits ...
85 lines
3.8 KiB
C
85 lines
3.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Interface the pinmux subsystem
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*
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* Copyright (C) 2011 ST-Ericsson SA
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* Written on behalf of Linaro for ST-Ericsson
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* Based on bits of regulator core, gpio core and clk core
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*
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* Author: Linus Walleij <linus.walleij@linaro.org>
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*/
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#ifndef __LINUX_PINCTRL_PINMUX_H
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#define __LINUX_PINCTRL_PINMUX_H
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#include <linux/list.h>
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#include <linux/seq_file.h>
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#include <linux/pinctrl/pinctrl.h>
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struct pinctrl_dev;
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/**
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* struct pinmux_ops - pinmux operations, to be implemented by pin controller
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* drivers that support pinmuxing
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* @request: called by the core to see if a certain pin can be made
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* available for muxing. This is called by the core to acquire the pins
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* before selecting any actual mux setting across a function. The driver
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* is allowed to answer "no" by returning a negative error code
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* @free: the reverse function of the request() callback, frees a pin after
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* being requested
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* @get_functions_count: returns number of selectable named functions available
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* in this pinmux driver
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* @get_function_name: return the function name of the muxing selector,
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* called by the core to figure out which mux setting it shall map a
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* certain device to
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* @get_function_groups: return an array of groups names (in turn
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* referencing pins) connected to a certain function selector. The group
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* name can be used with the generic @pinctrl_ops to retrieve the
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* actual pins affected. The applicable groups will be returned in
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* @groups and the number of groups in @num_groups
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* @set_mux: enable a certain muxing function with a certain pin group. The
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* driver does not need to figure out whether enabling this function
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* conflicts some other use of the pins in that group, such collisions
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* are handled by the pinmux subsystem. The @func_selector selects a
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* certain function whereas @group_selector selects a certain set of pins
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* to be used. On simple controllers the latter argument may be ignored
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* @gpio_request_enable: requests and enables GPIO on a certain pin.
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* Implement this only if you can mux every pin individually as GPIO. The
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* affected GPIO range is passed along with an offset(pin number) into that
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* specific GPIO range - function selectors and pin groups are orthogonal
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* to this, the core will however make sure the pins do not collide.
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* @gpio_disable_free: free up GPIO muxing on a certain pin, the reverse of
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* @gpio_request_enable
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* @gpio_set_direction: Since controllers may need different configurations
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* depending on whether the GPIO is configured as input or output,
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* a direction selector function may be implemented as a backing
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* to the GPIO controllers that need pin muxing.
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* @strict: do not allow simultaneous use of the same pin for GPIO and another
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* function. Check both gpio_owner and mux_owner strictly before approving
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* the pin request.
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*/
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struct pinmux_ops {
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int (*request) (struct pinctrl_dev *pctldev, unsigned offset);
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int (*free) (struct pinctrl_dev *pctldev, unsigned offset);
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int (*get_functions_count) (struct pinctrl_dev *pctldev);
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const char *(*get_function_name) (struct pinctrl_dev *pctldev,
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unsigned selector);
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int (*get_function_groups) (struct pinctrl_dev *pctldev,
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unsigned selector,
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const char * const **groups,
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unsigned *num_groups);
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int (*set_mux) (struct pinctrl_dev *pctldev, unsigned func_selector,
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unsigned group_selector);
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int (*gpio_request_enable) (struct pinctrl_dev *pctldev,
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struct pinctrl_gpio_range *range,
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unsigned offset);
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void (*gpio_disable_free) (struct pinctrl_dev *pctldev,
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struct pinctrl_gpio_range *range,
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unsigned offset);
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int (*gpio_set_direction) (struct pinctrl_dev *pctldev,
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struct pinctrl_gpio_range *range,
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unsigned offset,
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bool input);
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bool strict;
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};
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#endif /* __LINUX_PINCTRL_PINMUX_H */
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