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Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details you should have received a copy of the gnu general public license along with this program if not write to the free software foundation inc 675 mass ave cambridge ma 02139 usa extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 441 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Michael Ellerman <mpe@ellerman.id.au> (powerpc) Reviewed-by: Richard Fontana <rfontana@redhat.com> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190520071858.739733335@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
87 lines
2.3 KiB
C
87 lines
2.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* mach-davinci/nand.h
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*
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* Copyright © 2006 Texas Instruments.
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*
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* Ported to 2.6.23 Copyright © 2008 by
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* Sander Huijsen <Shuijsen@optelecom-nkf.com>
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* Troy Kisky <troy.kisky@boundarydevices.com>
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* Dirk Behme <Dirk.Behme@gmail.com>
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*
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* --------------------------------------------------------------------------
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*/
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#ifndef __ARCH_ARM_DAVINCI_NAND_H
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#define __ARCH_ARM_DAVINCI_NAND_H
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#include <linux/mtd/rawnand.h>
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#define NANDFCR_OFFSET 0x60
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#define NANDFSR_OFFSET 0x64
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#define NANDF1ECC_OFFSET 0x70
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/* 4-bit ECC syndrome registers */
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#define NAND_4BIT_ECC_LOAD_OFFSET 0xbc
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#define NAND_4BIT_ECC1_OFFSET 0xc0
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#define NAND_4BIT_ECC2_OFFSET 0xc4
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#define NAND_4BIT_ECC3_OFFSET 0xc8
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#define NAND_4BIT_ECC4_OFFSET 0xcc
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#define NAND_ERR_ADD1_OFFSET 0xd0
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#define NAND_ERR_ADD2_OFFSET 0xd4
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#define NAND_ERR_ERRVAL1_OFFSET 0xd8
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#define NAND_ERR_ERRVAL2_OFFSET 0xdc
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/* NOTE: boards don't need to use these address bits
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* for ALE/CLE unless they support booting from NAND.
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* They're used unless platform data overrides them.
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*/
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#define MASK_ALE 0x08
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#define MASK_CLE 0x10
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struct davinci_nand_pdata { /* platform_data */
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uint32_t mask_ale;
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uint32_t mask_cle;
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/*
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* 0-indexed chip-select number of the asynchronous
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* interface to which the NAND device has been connected.
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*
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* So, if you have NAND connected to CS3 of DA850, you
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* will pass '1' here. Since the asynchronous interface
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* on DA850 starts from CS2.
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*/
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uint32_t core_chipsel;
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/* for packages using two chipselects */
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uint32_t mask_chipsel;
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/* board's default static partition info */
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struct mtd_partition *parts;
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unsigned nr_parts;
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/* none == NAND_ECC_NONE (strongly *not* advised!!)
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* soft == NAND_ECC_SOFT
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* else == NAND_ECC_HW, according to ecc_bits
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*
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* All DaVinci-family chips support 1-bit hardware ECC.
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* Newer ones also support 4-bit ECC, but are awkward
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* using it with large page chips.
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*/
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nand_ecc_modes_t ecc_mode;
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u8 ecc_bits;
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/* e.g. NAND_BUSWIDTH_16 */
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unsigned options;
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/* e.g. NAND_BBT_USE_FLASH */
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unsigned bbt_options;
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/* Main and mirror bbt descriptor overrides */
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struct nand_bbt_descr *bbt_td;
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struct nand_bbt_descr *bbt_md;
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/* Access timings */
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struct davinci_aemif_timing *timing;
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};
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#endif /* __ARCH_ARM_DAVINCI_NAND_H */
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