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6158231a84
The pwm-crc code is using 2 different enable bits: 1. bit 7 of the PWM0_CLK_DIV (PWM_OUTPUT_ENABLE) 2. bit 0 of the BACKLIGHT_EN register The BACKLIGHT_EN register at address 0x51 really controls a separate output-only GPIO which is earmarked to be used as output connected to the backlight-enable pin for LCD panels, this GPO is part of the PMIC's "Display Panel Control Block." . This pin should probably be moved over to a GPIO provider driver (and consumers modified accordingly), but that is something for an(other) patch. Enabling / disabling the actual PWM output is controlled by the PWM_OUTPUT_ENABLE bit of the PWM0_CLK_DIV register. As the comment in the old code already indicates we must disable the PWM before we can change the clock divider. But the crc_pwm_disable() and crc_pwm_enable() calls the old code make for this only change the BACKLIGHT_EN register; and the value of that register does not matter for changing the period / the divider. What does matter is that the PWM_OUTPUT_ENABLE bit must be cleared before a new value can be written. This commit modifies crc_pwm_config() to clear PWM_OUTPUT_ENABLE instead when changing the period, so that period changes actually work. Note this fix will cause a significant behavior change on some devices using the CRC PWM output to drive their backlight. Before the PWM would always run with the output frequency configured by the BIOS at boot, now the period time specified by the i915 driver will actually be honored. Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Thierry Reding <thierry.reding@gmail.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200903112337.4113-11-hdegoede@redhat.com
143 lines
3.4 KiB
C
143 lines
3.4 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2015 Intel Corporation. All rights reserved.
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*
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* Author: Shobhit Kumar <shobhit.kumar@intel.com>
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*/
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/mfd/intel_soc_pmic.h>
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#include <linux/pwm.h>
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#define PWM0_CLK_DIV 0x4B
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#define PWM_OUTPUT_ENABLE BIT(7)
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#define PWM_DIV_CLK_0 0x00 /* DIVIDECLK = BASECLK */
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#define PWM_DIV_CLK_100 0x63 /* DIVIDECLK = BASECLK/100 */
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#define PWM_DIV_CLK_128 0x7F /* DIVIDECLK = BASECLK/128 */
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#define PWM0_DUTY_CYCLE 0x4E
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#define BACKLIGHT_EN 0x51
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#define PWM_MAX_LEVEL 0xFF
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#define PWM_BASE_CLK_MHZ 6 /* 6 MHz */
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#define PWM_MAX_PERIOD_NS 5461334 /* 183 Hz */
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/**
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* struct crystalcove_pwm - Crystal Cove PWM controller
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* @chip: the abstract pwm_chip structure.
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* @regmap: the regmap from the parent device.
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*/
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struct crystalcove_pwm {
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struct pwm_chip chip;
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struct regmap *regmap;
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};
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static inline struct crystalcove_pwm *to_crc_pwm(struct pwm_chip *pc)
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{
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return container_of(pc, struct crystalcove_pwm, chip);
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}
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static int crc_pwm_calc_clk_div(int period_ns)
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{
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int clk_div;
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clk_div = PWM_BASE_CLK_MHZ * period_ns / (256 * NSEC_PER_USEC);
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/* clk_div 1 - 128, maps to register values 0-127 */
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if (clk_div > 0)
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clk_div--;
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return clk_div;
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}
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static int crc_pwm_enable(struct pwm_chip *c, struct pwm_device *pwm)
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{
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struct crystalcove_pwm *crc_pwm = to_crc_pwm(c);
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regmap_write(crc_pwm->regmap, BACKLIGHT_EN, 1);
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return 0;
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}
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static void crc_pwm_disable(struct pwm_chip *c, struct pwm_device *pwm)
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{
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struct crystalcove_pwm *crc_pwm = to_crc_pwm(c);
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regmap_write(crc_pwm->regmap, BACKLIGHT_EN, 0);
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}
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static int crc_pwm_config(struct pwm_chip *c, struct pwm_device *pwm,
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int duty_ns, int period_ns)
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{
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struct crystalcove_pwm *crc_pwm = to_crc_pwm(c);
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struct device *dev = crc_pwm->chip.dev;
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int level;
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if (period_ns > PWM_MAX_PERIOD_NS) {
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dev_err(dev, "un-supported period_ns\n");
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return -EINVAL;
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}
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if (pwm_get_period(pwm) != period_ns) {
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int clk_div = crc_pwm_calc_clk_div(period_ns);
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/* changing the clk divisor, clear PWM_OUTPUT_ENABLE first */
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regmap_write(crc_pwm->regmap, PWM0_CLK_DIV, 0);
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regmap_write(crc_pwm->regmap, PWM0_CLK_DIV,
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clk_div | PWM_OUTPUT_ENABLE);
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}
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/* change the pwm duty cycle */
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level = duty_ns * PWM_MAX_LEVEL / period_ns;
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regmap_write(crc_pwm->regmap, PWM0_DUTY_CYCLE, level);
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return 0;
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}
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static const struct pwm_ops crc_pwm_ops = {
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.config = crc_pwm_config,
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.enable = crc_pwm_enable,
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.disable = crc_pwm_disable,
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};
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static int crystalcove_pwm_probe(struct platform_device *pdev)
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{
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struct crystalcove_pwm *pwm;
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struct device *dev = pdev->dev.parent;
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struct intel_soc_pmic *pmic = dev_get_drvdata(dev);
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pwm = devm_kzalloc(&pdev->dev, sizeof(*pwm), GFP_KERNEL);
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if (!pwm)
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return -ENOMEM;
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pwm->chip.dev = &pdev->dev;
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pwm->chip.ops = &crc_pwm_ops;
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pwm->chip.base = -1;
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pwm->chip.npwm = 1;
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/* get the PMIC regmap */
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pwm->regmap = pmic->regmap;
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platform_set_drvdata(pdev, pwm);
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return pwmchip_add(&pwm->chip);
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}
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static int crystalcove_pwm_remove(struct platform_device *pdev)
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{
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struct crystalcove_pwm *pwm = platform_get_drvdata(pdev);
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return pwmchip_remove(&pwm->chip);
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}
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static struct platform_driver crystalcove_pwm_driver = {
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.probe = crystalcove_pwm_probe,
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.remove = crystalcove_pwm_remove,
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.driver = {
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.name = "crystal_cove_pwm",
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},
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};
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builtin_platform_driver(crystalcove_pwm_driver);
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