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![Grant Likely](/assets/img/avatar_default.png)
Sort the gpio makefile and enforce the naming convention gpio-*.c for gpio drivers. v2: cleaned up filenames in Kconfig and comment blocks v3: fixup use of BASIC_MMIO to GENERIC_GPIO for mxc Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
408 lines
11 KiB
C
408 lines
11 KiB
C
/*
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* Generic EP93xx GPIO handling
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*
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* Copyright (c) 2008 Ryan Mallon <ryan@bluewatersys.com>
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*
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* Based on code originally from:
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* linux/arch/arm/mach-ep93xx/core.c
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#define pr_fmt(fmt) "ep93xx " KBUILD_MODNAME ": " fmt
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/seq_file.h>
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#include <linux/io.h>
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#include <linux/gpio.h>
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#include <linux/irq.h>
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#include <mach/hardware.h>
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/*************************************************************************
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* Interrupt handling for EP93xx on-chip GPIOs
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*************************************************************************/
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static unsigned char gpio_int_unmasked[3];
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static unsigned char gpio_int_enabled[3];
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static unsigned char gpio_int_type1[3];
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static unsigned char gpio_int_type2[3];
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static unsigned char gpio_int_debounce[3];
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/* Port ordering is: A B F */
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static const u8 int_type1_register_offset[3] = { 0x90, 0xac, 0x4c };
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static const u8 int_type2_register_offset[3] = { 0x94, 0xb0, 0x50 };
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static const u8 eoi_register_offset[3] = { 0x98, 0xb4, 0x54 };
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static const u8 int_en_register_offset[3] = { 0x9c, 0xb8, 0x58 };
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static const u8 int_debounce_register_offset[3] = { 0xa8, 0xc4, 0x64 };
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static void ep93xx_gpio_update_int_params(unsigned port)
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{
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BUG_ON(port > 2);
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__raw_writeb(0, EP93XX_GPIO_REG(int_en_register_offset[port]));
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__raw_writeb(gpio_int_type2[port],
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EP93XX_GPIO_REG(int_type2_register_offset[port]));
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__raw_writeb(gpio_int_type1[port],
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EP93XX_GPIO_REG(int_type1_register_offset[port]));
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__raw_writeb(gpio_int_unmasked[port] & gpio_int_enabled[port],
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EP93XX_GPIO_REG(int_en_register_offset[port]));
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}
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static inline void ep93xx_gpio_int_mask(unsigned line)
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{
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gpio_int_unmasked[line >> 3] &= ~(1 << (line & 7));
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}
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static void ep93xx_gpio_int_debounce(unsigned int irq, bool enable)
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{
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int line = irq_to_gpio(irq);
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int port = line >> 3;
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int port_mask = 1 << (line & 7);
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if (enable)
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gpio_int_debounce[port] |= port_mask;
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else
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gpio_int_debounce[port] &= ~port_mask;
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__raw_writeb(gpio_int_debounce[port],
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EP93XX_GPIO_REG(int_debounce_register_offset[port]));
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}
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static void ep93xx_gpio_ab_irq_handler(unsigned int irq, struct irq_desc *desc)
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{
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unsigned char status;
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int i;
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status = __raw_readb(EP93XX_GPIO_A_INT_STATUS);
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for (i = 0; i < 8; i++) {
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if (status & (1 << i)) {
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int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_A(0)) + i;
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generic_handle_irq(gpio_irq);
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}
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}
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status = __raw_readb(EP93XX_GPIO_B_INT_STATUS);
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for (i = 0; i < 8; i++) {
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if (status & (1 << i)) {
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int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_B(0)) + i;
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generic_handle_irq(gpio_irq);
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}
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}
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}
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static void ep93xx_gpio_f_irq_handler(unsigned int irq, struct irq_desc *desc)
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{
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/*
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* map discontiguous hw irq range to continuous sw irq range:
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*
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* IRQ_EP93XX_GPIO{0..7}MUX -> gpio_to_irq(EP93XX_GPIO_LINE_F({0..7})
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*/
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int port_f_idx = ((irq + 1) & 7) ^ 4; /* {19..22,47..50} -> {0..7} */
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int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_F(0)) + port_f_idx;
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generic_handle_irq(gpio_irq);
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}
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static void ep93xx_gpio_irq_ack(struct irq_data *d)
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{
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int line = irq_to_gpio(d->irq);
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int port = line >> 3;
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int port_mask = 1 << (line & 7);
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if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) {
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gpio_int_type2[port] ^= port_mask; /* switch edge direction */
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ep93xx_gpio_update_int_params(port);
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}
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__raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
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}
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static void ep93xx_gpio_irq_mask_ack(struct irq_data *d)
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{
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int line = irq_to_gpio(d->irq);
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int port = line >> 3;
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int port_mask = 1 << (line & 7);
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if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH)
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gpio_int_type2[port] ^= port_mask; /* switch edge direction */
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gpio_int_unmasked[port] &= ~port_mask;
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ep93xx_gpio_update_int_params(port);
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__raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
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}
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static void ep93xx_gpio_irq_mask(struct irq_data *d)
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{
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int line = irq_to_gpio(d->irq);
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int port = line >> 3;
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gpio_int_unmasked[port] &= ~(1 << (line & 7));
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ep93xx_gpio_update_int_params(port);
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}
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static void ep93xx_gpio_irq_unmask(struct irq_data *d)
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{
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int line = irq_to_gpio(d->irq);
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int port = line >> 3;
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gpio_int_unmasked[port] |= 1 << (line & 7);
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ep93xx_gpio_update_int_params(port);
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}
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/*
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* gpio_int_type1 controls whether the interrupt is level (0) or
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* edge (1) triggered, while gpio_int_type2 controls whether it
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* triggers on low/falling (0) or high/rising (1).
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*/
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static int ep93xx_gpio_irq_type(struct irq_data *d, unsigned int type)
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{
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const int gpio = irq_to_gpio(d->irq);
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const int port = gpio >> 3;
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const int port_mask = 1 << (gpio & 7);
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irq_flow_handler_t handler;
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gpio_direction_input(gpio);
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switch (type) {
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case IRQ_TYPE_EDGE_RISING:
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gpio_int_type1[port] |= port_mask;
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gpio_int_type2[port] |= port_mask;
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handler = handle_edge_irq;
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break;
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case IRQ_TYPE_EDGE_FALLING:
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gpio_int_type1[port] |= port_mask;
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gpio_int_type2[port] &= ~port_mask;
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handler = handle_edge_irq;
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break;
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case IRQ_TYPE_LEVEL_HIGH:
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gpio_int_type1[port] &= ~port_mask;
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gpio_int_type2[port] |= port_mask;
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handler = handle_level_irq;
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break;
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case IRQ_TYPE_LEVEL_LOW:
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gpio_int_type1[port] &= ~port_mask;
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gpio_int_type2[port] &= ~port_mask;
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handler = handle_level_irq;
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break;
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case IRQ_TYPE_EDGE_BOTH:
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gpio_int_type1[port] |= port_mask;
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/* set initial polarity based on current input level */
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if (gpio_get_value(gpio))
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gpio_int_type2[port] &= ~port_mask; /* falling */
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else
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gpio_int_type2[port] |= port_mask; /* rising */
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handler = handle_edge_irq;
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break;
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default:
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pr_err("failed to set irq type %d for gpio %d\n", type, gpio);
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return -EINVAL;
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}
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__irq_set_handler_locked(d->irq, handler);
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gpio_int_enabled[port] |= port_mask;
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ep93xx_gpio_update_int_params(port);
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return 0;
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}
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static struct irq_chip ep93xx_gpio_irq_chip = {
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.name = "GPIO",
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.irq_ack = ep93xx_gpio_irq_ack,
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.irq_mask_ack = ep93xx_gpio_irq_mask_ack,
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.irq_mask = ep93xx_gpio_irq_mask,
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.irq_unmask = ep93xx_gpio_irq_unmask,
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.irq_set_type = ep93xx_gpio_irq_type,
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};
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void __init ep93xx_gpio_init_irq(void)
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{
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int gpio_irq;
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for (gpio_irq = gpio_to_irq(0);
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gpio_irq <= gpio_to_irq(EP93XX_GPIO_LINE_MAX_IRQ); ++gpio_irq) {
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irq_set_chip_and_handler(gpio_irq, &ep93xx_gpio_irq_chip,
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handle_level_irq);
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set_irq_flags(gpio_irq, IRQF_VALID);
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}
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irq_set_chained_handler(IRQ_EP93XX_GPIO_AB,
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ep93xx_gpio_ab_irq_handler);
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irq_set_chained_handler(IRQ_EP93XX_GPIO0MUX,
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ep93xx_gpio_f_irq_handler);
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irq_set_chained_handler(IRQ_EP93XX_GPIO1MUX,
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ep93xx_gpio_f_irq_handler);
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irq_set_chained_handler(IRQ_EP93XX_GPIO2MUX,
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ep93xx_gpio_f_irq_handler);
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irq_set_chained_handler(IRQ_EP93XX_GPIO3MUX,
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ep93xx_gpio_f_irq_handler);
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irq_set_chained_handler(IRQ_EP93XX_GPIO4MUX,
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ep93xx_gpio_f_irq_handler);
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irq_set_chained_handler(IRQ_EP93XX_GPIO5MUX,
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ep93xx_gpio_f_irq_handler);
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irq_set_chained_handler(IRQ_EP93XX_GPIO6MUX,
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ep93xx_gpio_f_irq_handler);
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irq_set_chained_handler(IRQ_EP93XX_GPIO7MUX,
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ep93xx_gpio_f_irq_handler);
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}
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/*************************************************************************
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* gpiolib interface for EP93xx on-chip GPIOs
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*************************************************************************/
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struct ep93xx_gpio_chip {
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struct gpio_chip chip;
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void __iomem *data_reg;
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void __iomem *data_dir_reg;
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};
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#define to_ep93xx_gpio_chip(c) container_of(c, struct ep93xx_gpio_chip, chip)
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static int ep93xx_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
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{
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struct ep93xx_gpio_chip *ep93xx_chip = to_ep93xx_gpio_chip(chip);
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unsigned long flags;
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u8 v;
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local_irq_save(flags);
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v = __raw_readb(ep93xx_chip->data_dir_reg);
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v &= ~(1 << offset);
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__raw_writeb(v, ep93xx_chip->data_dir_reg);
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local_irq_restore(flags);
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return 0;
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}
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static int ep93xx_gpio_direction_output(struct gpio_chip *chip,
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unsigned offset, int val)
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{
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struct ep93xx_gpio_chip *ep93xx_chip = to_ep93xx_gpio_chip(chip);
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unsigned long flags;
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int line;
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u8 v;
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local_irq_save(flags);
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/* Set the value */
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v = __raw_readb(ep93xx_chip->data_reg);
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if (val)
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v |= (1 << offset);
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else
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v &= ~(1 << offset);
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__raw_writeb(v, ep93xx_chip->data_reg);
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/* Drive as an output */
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line = chip->base + offset;
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if (line <= EP93XX_GPIO_LINE_MAX_IRQ) {
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/* Ports A/B/F */
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ep93xx_gpio_int_mask(line);
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ep93xx_gpio_update_int_params(line >> 3);
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}
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v = __raw_readb(ep93xx_chip->data_dir_reg);
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v |= (1 << offset);
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__raw_writeb(v, ep93xx_chip->data_dir_reg);
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local_irq_restore(flags);
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return 0;
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}
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static int ep93xx_gpio_get(struct gpio_chip *chip, unsigned offset)
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{
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struct ep93xx_gpio_chip *ep93xx_chip = to_ep93xx_gpio_chip(chip);
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return !!(__raw_readb(ep93xx_chip->data_reg) & (1 << offset));
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}
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static void ep93xx_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
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{
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struct ep93xx_gpio_chip *ep93xx_chip = to_ep93xx_gpio_chip(chip);
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unsigned long flags;
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u8 v;
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local_irq_save(flags);
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v = __raw_readb(ep93xx_chip->data_reg);
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if (val)
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v |= (1 << offset);
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else
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v &= ~(1 << offset);
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__raw_writeb(v, ep93xx_chip->data_reg);
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local_irq_restore(flags);
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}
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static int ep93xx_gpio_set_debounce(struct gpio_chip *chip,
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unsigned offset, unsigned debounce)
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{
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int gpio = chip->base + offset;
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int irq = gpio_to_irq(gpio);
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if (irq < 0)
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return -EINVAL;
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ep93xx_gpio_int_debounce(irq, debounce ? true : false);
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return 0;
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}
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#define EP93XX_GPIO_BANK(name, dr, ddr, base_gpio) \
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{ \
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.chip = { \
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.label = name, \
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.direction_input = ep93xx_gpio_direction_input, \
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.direction_output = ep93xx_gpio_direction_output, \
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.get = ep93xx_gpio_get, \
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.set = ep93xx_gpio_set, \
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.base = base_gpio, \
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.ngpio = 8, \
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}, \
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.data_reg = EP93XX_GPIO_REG(dr), \
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.data_dir_reg = EP93XX_GPIO_REG(ddr), \
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}
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static struct ep93xx_gpio_chip ep93xx_gpio_banks[] = {
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EP93XX_GPIO_BANK("A", 0x00, 0x10, 0),
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EP93XX_GPIO_BANK("B", 0x04, 0x14, 8),
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EP93XX_GPIO_BANK("C", 0x08, 0x18, 40),
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EP93XX_GPIO_BANK("D", 0x0c, 0x1c, 24),
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EP93XX_GPIO_BANK("E", 0x20, 0x24, 32),
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EP93XX_GPIO_BANK("F", 0x30, 0x34, 16),
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EP93XX_GPIO_BANK("G", 0x38, 0x3c, 48),
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EP93XX_GPIO_BANK("H", 0x40, 0x44, 56),
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};
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void __init ep93xx_gpio_init(void)
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{
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int i;
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/* Set Ports C, D, E, G, and H for GPIO use */
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ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_KEYS |
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EP93XX_SYSCON_DEVCFG_GONK |
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EP93XX_SYSCON_DEVCFG_EONIDE |
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EP93XX_SYSCON_DEVCFG_GONIDE |
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EP93XX_SYSCON_DEVCFG_HONIDE);
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for (i = 0; i < ARRAY_SIZE(ep93xx_gpio_banks); i++) {
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struct gpio_chip *chip = &ep93xx_gpio_banks[i].chip;
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/*
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* Ports A, B, and F support input debouncing when
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* used as interrupts.
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*/
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if (!strcmp(chip->label, "A") ||
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!strcmp(chip->label, "B") ||
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!strcmp(chip->label, "F"))
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chip->set_debounce = ep93xx_gpio_set_debounce;
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gpiochip_add(chip);
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}
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}
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