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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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2ce7c62d1b
Memory for basic-mmio-gpio driver is allocated by the driver using it, whether it's the generic GPIO driver itself or another driver. In either case, the owner shall allocate and free the struct bgpio_chip it is using, preferably using a managed resource. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
573 lines
14 KiB
C
573 lines
14 KiB
C
/*
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* Generic driver for memory-mapped GPIO controllers.
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*
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* Copyright 2008 MontaVista Software, Inc.
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* Copyright 2008,2010 Anton Vorontsov <cbouatmailru@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* ....``.```~~~~````.`.`.`.`.```````'',,,.........`````......`.......
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* ...`` ```````..
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* ..The simplest form of a GPIO controller that the driver supports is``
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* `.just a single "data" register, where GPIO state can be read and/or `
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* `,..written. ,,..``~~~~ .....``.`.`.~~.```.`.........``````.```````
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* `````````
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___
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_/~~|___/~| . ```~~~~~~ ___/___\___ ,~.`.`.`.`````.~~...,,,,...
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__________|~$@~~~ %~ /o*o*o*o*o*o\ .. Implementing such a GPIO .
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o ` ~~~~\___/~~~~ ` controller in FPGA is ,.`
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`....trivial..'~`.```.```
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* ```````
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* .```````~~~~`..`.``.``.
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* . The driver supports `... ,..```.`~~~```````````````....````.``,,
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* . big-endian notation, just`. .. A bit more sophisticated controllers ,
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* . register the device with -be`. .with a pair of set/clear-bit registers ,
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* `.. suffix. ```~~`````....`.` . affecting the data register and the .`
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* ``.`.``...``` ```.. output pins are also supported.`
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* ^^ `````.`````````.,``~``~``~~``````
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* . ^^
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* ,..`.`.`...````````````......`.`.`.`.`.`..`.`.`..
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* .. The expectation is that in at least some cases . ,-~~~-,
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* .this will be used with roll-your-own ASIC/FPGA .` \ /
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* .logic in Verilog or VHDL. ~~~`````````..`````~~` \ /
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* ..````````......``````````` \o_
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* |
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* ^^ / \
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*
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* ...`````~~`.....``.`..........``````.`.``.```........``.
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* ` 8, 16, 32 and 64 bits registers are supported, and``.
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* . the number of GPIOs is determined by the width of ~
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* .. the registers. ,............```.`.`..`.`.~~~.`.`.`~
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* `.......````.```
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*/
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#include <linux/init.h>
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#include <linux/err.h>
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#include <linux/bug.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/spinlock.h>
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#include <linux/compiler.h>
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#include <linux/types.h>
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#include <linux/errno.h>
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#include <linux/log2.h>
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#include <linux/ioport.h>
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#include <linux/io.h>
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#include <linux/gpio.h>
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#include <linux/slab.h>
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#include <linux/platform_device.h>
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#include <linux/mod_devicetable.h>
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#include <linux/basic_mmio_gpio.h>
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static void bgpio_write8(void __iomem *reg, unsigned long data)
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{
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writeb(data, reg);
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}
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static unsigned long bgpio_read8(void __iomem *reg)
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{
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return readb(reg);
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}
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static void bgpio_write16(void __iomem *reg, unsigned long data)
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{
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writew(data, reg);
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}
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static unsigned long bgpio_read16(void __iomem *reg)
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{
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return readw(reg);
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}
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static void bgpio_write32(void __iomem *reg, unsigned long data)
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{
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writel(data, reg);
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}
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static unsigned long bgpio_read32(void __iomem *reg)
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{
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return readl(reg);
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}
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#if BITS_PER_LONG >= 64
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static void bgpio_write64(void __iomem *reg, unsigned long data)
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{
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writeq(data, reg);
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}
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static unsigned long bgpio_read64(void __iomem *reg)
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{
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return readq(reg);
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}
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#endif /* BITS_PER_LONG >= 64 */
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static void bgpio_write16be(void __iomem *reg, unsigned long data)
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{
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iowrite16be(data, reg);
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}
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static unsigned long bgpio_read16be(void __iomem *reg)
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{
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return ioread16be(reg);
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}
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static void bgpio_write32be(void __iomem *reg, unsigned long data)
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{
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iowrite32be(data, reg);
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}
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static unsigned long bgpio_read32be(void __iomem *reg)
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{
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return ioread32be(reg);
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}
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static unsigned long bgpio_pin2mask(struct bgpio_chip *bgc, unsigned int pin)
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{
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return 1 << pin;
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}
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static unsigned long bgpio_pin2mask_be(struct bgpio_chip *bgc,
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unsigned int pin)
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{
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return 1 << (bgc->bits - 1 - pin);
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}
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static int bgpio_get(struct gpio_chip *gc, unsigned int gpio)
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{
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struct bgpio_chip *bgc = to_bgpio_chip(gc);
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return bgc->read_reg(bgc->reg_dat) & bgc->pin2mask(bgc, gpio);
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}
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static void bgpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
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{
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struct bgpio_chip *bgc = to_bgpio_chip(gc);
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unsigned long mask = bgc->pin2mask(bgc, gpio);
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unsigned long flags;
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spin_lock_irqsave(&bgc->lock, flags);
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if (val)
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bgc->data |= mask;
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else
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bgc->data &= ~mask;
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bgc->write_reg(bgc->reg_dat, bgc->data);
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spin_unlock_irqrestore(&bgc->lock, flags);
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}
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static void bgpio_set_with_clear(struct gpio_chip *gc, unsigned int gpio,
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int val)
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{
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struct bgpio_chip *bgc = to_bgpio_chip(gc);
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unsigned long mask = bgc->pin2mask(bgc, gpio);
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if (val)
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bgc->write_reg(bgc->reg_set, mask);
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else
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bgc->write_reg(bgc->reg_clr, mask);
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}
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static void bgpio_set_set(struct gpio_chip *gc, unsigned int gpio, int val)
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{
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struct bgpio_chip *bgc = to_bgpio_chip(gc);
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unsigned long mask = bgc->pin2mask(bgc, gpio);
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unsigned long flags;
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spin_lock_irqsave(&bgc->lock, flags);
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if (val)
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bgc->data |= mask;
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else
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bgc->data &= ~mask;
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bgc->write_reg(bgc->reg_set, bgc->data);
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spin_unlock_irqrestore(&bgc->lock, flags);
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}
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static int bgpio_simple_dir_in(struct gpio_chip *gc, unsigned int gpio)
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{
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return 0;
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}
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static int bgpio_simple_dir_out(struct gpio_chip *gc, unsigned int gpio,
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int val)
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{
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gc->set(gc, gpio, val);
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return 0;
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}
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static int bgpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
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{
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struct bgpio_chip *bgc = to_bgpio_chip(gc);
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unsigned long flags;
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spin_lock_irqsave(&bgc->lock, flags);
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bgc->dir &= ~bgc->pin2mask(bgc, gpio);
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bgc->write_reg(bgc->reg_dir, bgc->dir);
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spin_unlock_irqrestore(&bgc->lock, flags);
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return 0;
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}
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static int bgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
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{
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struct bgpio_chip *bgc = to_bgpio_chip(gc);
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unsigned long flags;
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gc->set(gc, gpio, val);
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spin_lock_irqsave(&bgc->lock, flags);
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bgc->dir |= bgc->pin2mask(bgc, gpio);
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bgc->write_reg(bgc->reg_dir, bgc->dir);
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spin_unlock_irqrestore(&bgc->lock, flags);
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return 0;
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}
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static int bgpio_dir_in_inv(struct gpio_chip *gc, unsigned int gpio)
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{
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struct bgpio_chip *bgc = to_bgpio_chip(gc);
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unsigned long flags;
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spin_lock_irqsave(&bgc->lock, flags);
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bgc->dir |= bgc->pin2mask(bgc, gpio);
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bgc->write_reg(bgc->reg_dir, bgc->dir);
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spin_unlock_irqrestore(&bgc->lock, flags);
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return 0;
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}
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static int bgpio_dir_out_inv(struct gpio_chip *gc, unsigned int gpio, int val)
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{
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struct bgpio_chip *bgc = to_bgpio_chip(gc);
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unsigned long flags;
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gc->set(gc, gpio, val);
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spin_lock_irqsave(&bgc->lock, flags);
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bgc->dir &= ~bgc->pin2mask(bgc, gpio);
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bgc->write_reg(bgc->reg_dir, bgc->dir);
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spin_unlock_irqrestore(&bgc->lock, flags);
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return 0;
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}
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static int bgpio_setup_accessors(struct device *dev,
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struct bgpio_chip *bgc,
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bool bit_be,
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bool byte_be)
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{
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switch (bgc->bits) {
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case 8:
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bgc->read_reg = bgpio_read8;
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bgc->write_reg = bgpio_write8;
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break;
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case 16:
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if (byte_be) {
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bgc->read_reg = bgpio_read16be;
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bgc->write_reg = bgpio_write16be;
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} else {
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bgc->read_reg = bgpio_read16;
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bgc->write_reg = bgpio_write16;
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}
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break;
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case 32:
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if (byte_be) {
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bgc->read_reg = bgpio_read32be;
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bgc->write_reg = bgpio_write32be;
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} else {
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bgc->read_reg = bgpio_read32;
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bgc->write_reg = bgpio_write32;
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}
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break;
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#if BITS_PER_LONG >= 64
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case 64:
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if (byte_be) {
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dev_err(dev,
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"64 bit big endian byte order unsupported\n");
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return -EINVAL;
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} else {
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bgc->read_reg = bgpio_read64;
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bgc->write_reg = bgpio_write64;
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}
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break;
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#endif /* BITS_PER_LONG >= 64 */
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default:
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dev_err(dev, "unsupported data width %u bits\n", bgc->bits);
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return -EINVAL;
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}
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bgc->pin2mask = bit_be ? bgpio_pin2mask_be : bgpio_pin2mask;
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return 0;
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}
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/*
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* Create the device and allocate the resources. For setting GPIO's there are
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* three supported configurations:
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*
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* - single input/output register resource (named "dat").
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* - set/clear pair (named "set" and "clr").
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* - single output register resource and single input resource ("set" and
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* dat").
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*
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* For the single output register, this drives a 1 by setting a bit and a zero
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* by clearing a bit. For the set clr pair, this drives a 1 by setting a bit
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* in the set register and clears it by setting a bit in the clear register.
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* The configuration is detected by which resources are present.
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*
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* For setting the GPIO direction, there are three supported configurations:
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*
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* - simple bidirection GPIO that requires no configuration.
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* - an output direction register (named "dirout") where a 1 bit
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* indicates the GPIO is an output.
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* - an input direction register (named "dirin") where a 1 bit indicates
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* the GPIO is an input.
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*/
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static int bgpio_setup_io(struct bgpio_chip *bgc,
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void __iomem *dat,
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void __iomem *set,
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void __iomem *clr)
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{
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bgc->reg_dat = dat;
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if (!bgc->reg_dat)
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return -EINVAL;
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if (set && clr) {
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bgc->reg_set = set;
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bgc->reg_clr = clr;
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bgc->gc.set = bgpio_set_with_clear;
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} else if (set && !clr) {
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bgc->reg_set = set;
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bgc->gc.set = bgpio_set_set;
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} else {
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bgc->gc.set = bgpio_set;
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}
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bgc->gc.get = bgpio_get;
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return 0;
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}
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static int bgpio_setup_direction(struct bgpio_chip *bgc,
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void __iomem *dirout,
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void __iomem *dirin)
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{
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if (dirout && dirin) {
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return -EINVAL;
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} else if (dirout) {
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bgc->reg_dir = dirout;
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bgc->gc.direction_output = bgpio_dir_out;
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bgc->gc.direction_input = bgpio_dir_in;
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} else if (dirin) {
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bgc->reg_dir = dirin;
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bgc->gc.direction_output = bgpio_dir_out_inv;
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bgc->gc.direction_input = bgpio_dir_in_inv;
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} else {
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bgc->gc.direction_output = bgpio_simple_dir_out;
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bgc->gc.direction_input = bgpio_simple_dir_in;
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}
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return 0;
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}
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int bgpio_remove(struct bgpio_chip *bgc)
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{
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return gpiochip_remove(&bgc->gc);
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}
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EXPORT_SYMBOL_GPL(bgpio_remove);
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int bgpio_init(struct bgpio_chip *bgc, struct device *dev,
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unsigned long sz, void __iomem *dat, void __iomem *set,
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void __iomem *clr, void __iomem *dirout, void __iomem *dirin,
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unsigned long flags)
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{
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int ret;
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if (!is_power_of_2(sz))
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return -EINVAL;
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bgc->bits = sz * 8;
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if (bgc->bits > BITS_PER_LONG)
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return -EINVAL;
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spin_lock_init(&bgc->lock);
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bgc->gc.dev = dev;
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bgc->gc.label = dev_name(dev);
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bgc->gc.base = -1;
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bgc->gc.ngpio = bgc->bits;
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ret = bgpio_setup_io(bgc, dat, set, clr);
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if (ret)
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return ret;
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ret = bgpio_setup_accessors(dev, bgc, flags & BGPIOF_BIG_ENDIAN,
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flags & BGPIOF_BIG_ENDIAN_BYTE_ORDER);
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if (ret)
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return ret;
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ret = bgpio_setup_direction(bgc, dirout, dirin);
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if (ret)
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return ret;
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bgc->data = bgc->read_reg(bgc->reg_dat);
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if (bgc->gc.set == bgpio_set_set &&
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!(flags & BGPIOF_UNREADABLE_REG_SET))
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bgc->data = bgc->read_reg(bgc->reg_set);
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if (bgc->reg_dir && !(flags & BGPIOF_UNREADABLE_REG_DIR))
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bgc->dir = bgc->read_reg(bgc->reg_dir);
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return ret;
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}
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EXPORT_SYMBOL_GPL(bgpio_init);
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#ifdef CONFIG_GPIO_GENERIC_PLATFORM
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static void __iomem *bgpio_map(struct platform_device *pdev,
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const char *name,
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resource_size_t sane_sz,
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int *err)
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{
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struct device *dev = &pdev->dev;
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struct resource *r;
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resource_size_t start;
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resource_size_t sz;
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void __iomem *ret;
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*err = 0;
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r = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
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if (!r)
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return NULL;
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sz = resource_size(r);
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if (sz != sane_sz) {
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*err = -EINVAL;
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return NULL;
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}
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start = r->start;
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if (!devm_request_mem_region(dev, start, sz, r->name)) {
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*err = -EBUSY;
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return NULL;
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}
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ret = devm_ioremap(dev, start, sz);
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if (!ret) {
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*err = -ENOMEM;
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return NULL;
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}
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return ret;
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}
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static int bgpio_pdev_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct resource *r;
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void __iomem *dat;
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void __iomem *set;
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void __iomem *clr;
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void __iomem *dirout;
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void __iomem *dirin;
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unsigned long sz;
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unsigned long flags = 0;
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int err;
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struct bgpio_chip *bgc;
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struct bgpio_pdata *pdata = dev_get_platdata(dev);
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r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat");
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if (!r)
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return -EINVAL;
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sz = resource_size(r);
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dat = bgpio_map(pdev, "dat", sz, &err);
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if (!dat)
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return err ? err : -EINVAL;
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set = bgpio_map(pdev, "set", sz, &err);
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if (err)
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return err;
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clr = bgpio_map(pdev, "clr", sz, &err);
|
|
if (err)
|
|
return err;
|
|
|
|
dirout = bgpio_map(pdev, "dirout", sz, &err);
|
|
if (err)
|
|
return err;
|
|
|
|
dirin = bgpio_map(pdev, "dirin", sz, &err);
|
|
if (err)
|
|
return err;
|
|
|
|
if (!strcmp(platform_get_device_id(pdev)->name, "basic-mmio-gpio-be"))
|
|
flags |= BGPIOF_BIG_ENDIAN;
|
|
|
|
bgc = devm_kzalloc(&pdev->dev, sizeof(*bgc), GFP_KERNEL);
|
|
if (!bgc)
|
|
return -ENOMEM;
|
|
|
|
err = bgpio_init(bgc, dev, sz, dat, set, clr, dirout, dirin, flags);
|
|
if (err)
|
|
return err;
|
|
|
|
if (pdata) {
|
|
bgc->gc.base = pdata->base;
|
|
if (pdata->ngpio > 0)
|
|
bgc->gc.ngpio = pdata->ngpio;
|
|
}
|
|
|
|
platform_set_drvdata(pdev, bgc);
|
|
|
|
return gpiochip_add(&bgc->gc);
|
|
}
|
|
|
|
static int bgpio_pdev_remove(struct platform_device *pdev)
|
|
{
|
|
struct bgpio_chip *bgc = platform_get_drvdata(pdev);
|
|
|
|
return bgpio_remove(bgc);
|
|
}
|
|
|
|
static const struct platform_device_id bgpio_id_table[] = {
|
|
{ "basic-mmio-gpio", },
|
|
{ "basic-mmio-gpio-be", },
|
|
{},
|
|
};
|
|
MODULE_DEVICE_TABLE(platform, bgpio_id_table);
|
|
|
|
static struct platform_driver bgpio_driver = {
|
|
.driver = {
|
|
.name = "basic-mmio-gpio",
|
|
},
|
|
.id_table = bgpio_id_table,
|
|
.probe = bgpio_pdev_probe,
|
|
.remove = bgpio_pdev_remove,
|
|
};
|
|
|
|
module_platform_driver(bgpio_driver);
|
|
|
|
#endif /* CONFIG_GPIO_GENERIC_PLATFORM */
|
|
|
|
MODULE_DESCRIPTION("Driver for basic memory-mapped GPIO controllers");
|
|
MODULE_AUTHOR("Anton Vorontsov <cbouatmailru@gmail.com>");
|
|
MODULE_LICENSE("GPL");
|