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![Huang Rui](/assets/img/avatar_default.png)
Introduce the AMD P-State driver design and implementation. Signed-off-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
382 lines
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ReStructuredText
382 lines
20 KiB
ReStructuredText
.. SPDX-License-Identifier: GPL-2.0
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.. include:: <isonum.txt>
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===============================================
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``amd-pstate`` CPU Performance Scaling Driver
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===============================================
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:Copyright: |copy| 2021 Advanced Micro Devices, Inc.
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:Author: Huang Rui <ray.huang@amd.com>
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Introduction
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===================
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``amd-pstate`` is the AMD CPU performance scaling driver that introduces a
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new CPU frequency control mechanism on modern AMD APU and CPU series in
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Linux kernel. The new mechanism is based on Collaborative Processor
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Performance Control (CPPC) which provides finer grain frequency management
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than legacy ACPI hardware P-States. Current AMD CPU/APU platforms are using
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the ACPI P-states driver to manage CPU frequency and clocks with switching
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only in 3 P-states. CPPC replaces the ACPI P-states controls, allows a
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flexible, low-latency interface for the Linux kernel to directly
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communicate the performance hints to hardware.
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``amd-pstate`` leverages the Linux kernel governors such as ``schedutil``,
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``ondemand``, etc. to manage the performance hints which are provided by
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CPPC hardware functionality that internally follows the hardware
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specification (for details refer to AMD64 Architecture Programmer's Manual
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Volume 2: System Programming [1]_). Currently ``amd-pstate`` supports basic
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frequency control function according to kernel governors on some of the
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Zen2 and Zen3 processors, and we will implement more AMD specific functions
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in future after we verify them on the hardware and SBIOS.
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AMD CPPC Overview
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=======================
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Collaborative Processor Performance Control (CPPC) interface enumerates a
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continuous, abstract, and unit-less performance value in a scale that is
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not tied to a specific performance state / frequency. This is an ACPI
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standard [2]_ which software can specify application performance goals and
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hints as a relative target to the infrastructure limits. AMD processors
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provides the low latency register model (MSR) instead of AML code
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interpreter for performance adjustments. ``amd-pstate`` will initialize a
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``struct cpufreq_driver`` instance ``amd_pstate_driver`` with the callbacks
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to manage each performance update behavior. ::
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Highest Perf ------>+-----------------------+ +-----------------------+
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| | Max Perf ---->| |
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Nominal Perf ------>+-----------------------+ +-----------------------+
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| | Desired Perf ---->| |
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Lowest non- | | | |
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linear perf ------>+-----------------------+ +-----------------------+
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| | Lowest perf ---->| |
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Lowest perf ------>+-----------------------+ +-----------------------+
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0 ------>+-----------------------+ +-----------------------+
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AMD P-States Performance Scale
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.. _perf_cap:
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AMD CPPC Performance Capability
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--------------------------------
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Highest Performance (RO)
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.........................
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It is the absolute maximum performance an individual processor may reach,
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assuming ideal conditions. This performance level may not be sustainable
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for long durations and may only be achievable if other platform components
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are in a specific state; for example, it may require other processors be in
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an idle state. This would be equivalent to the highest frequencies
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supported by the processor.
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Nominal (Guaranteed) Performance (RO)
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......................................
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It is the maximum sustained performance level of the processor, assuming
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ideal operating conditions. In absence of an external constraint (power,
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thermal, etc.) this is the performance level the processor is expected to
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be able to maintain continuously. All cores/processors are expected to be
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able to sustain their nominal performance state simultaneously.
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Lowest non-linear Performance (RO)
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...................................
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It is the lowest performance level at which nonlinear power savings are
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achieved, for example, due to the combined effects of voltage and frequency
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scaling. Above this threshold, lower performance levels should be generally
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more energy efficient than higher performance levels. This register
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effectively conveys the most efficient performance level to ``amd-pstate``.
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Lowest Performance (RO)
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........................
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It is the absolute lowest performance level of the processor. Selecting a
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performance level lower than the lowest nonlinear performance level may
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cause an efficiency penalty but should reduce the instantaneous power
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consumption of the processor.
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AMD CPPC Performance Control
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------------------------------
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``amd-pstate`` passes performance goals through these registers. The
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register drives the behavior of the desired performance target.
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Minimum requested performance (RW)
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...................................
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``amd-pstate`` specifies the minimum allowed performance level.
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Maximum requested performance (RW)
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...................................
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``amd-pstate`` specifies a limit the maximum performance that is expected
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to be supplied by the hardware.
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Desired performance target (RW)
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...................................
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``amd-pstate`` specifies a desired target in the CPPC performance scale as
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a relative number. This can be expressed as percentage of nominal
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performance (infrastructure max). Below the nominal sustained performance
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level, desired performance expresses the average performance level of the
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processor subject to hardware. Above the nominal performance level,
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processor must provide at least nominal performance requested and go higher
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if current operating conditions allow.
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Energy Performance Preference (EPP) (RW)
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.........................................
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Provides a hint to the hardware if software wants to bias toward performance
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(0x0) or energy efficiency (0xff).
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Key Governors Support
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=======================
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``amd-pstate`` can be used with all the (generic) scaling governors listed
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by the ``scaling_available_governors`` policy attribute in ``sysfs``. Then,
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it is responsible for the configuration of policy objects corresponding to
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CPUs and provides the ``CPUFreq`` core (and the scaling governors attached
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to the policy objects) with accurate information on the maximum and minimum
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operating frequencies supported by the hardware. Users can check the
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``scaling_cur_freq`` information comes from the ``CPUFreq`` core.
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``amd-pstate`` mainly supports ``schedutil`` and ``ondemand`` for dynamic
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frequency control. It is to fine tune the processor configuration on
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``amd-pstate`` to the ``schedutil`` with CPU CFS scheduler. ``amd-pstate``
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registers adjust_perf callback to implement the CPPC similar performance
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update behavior. It is initialized by ``sugov_start`` and then populate the
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CPU's update_util_data pointer to assign ``sugov_update_single_perf`` as
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the utilization update callback function in CPU scheduler. CPU scheduler
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will call ``cpufreq_update_util`` and assign the target performance
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according to the ``struct sugov_cpu`` that utilization update belongs to.
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Then ``amd-pstate`` updates the desired performance according to the CPU
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scheduler assigned.
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Processor Support
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=======================
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The ``amd-pstate`` initialization will fail if the _CPC in ACPI SBIOS is
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not existed at the detected processor, and it uses ``acpi_cpc_valid`` to
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check the _CPC existence. All Zen based processors support legacy ACPI
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hardware P-States function, so while the ``amd-pstate`` fails to be
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initialized, the kernel will fall back to initialize ``acpi-cpufreq``
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driver.
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There are two types of hardware implementations for ``amd-pstate``: one is
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`Full MSR Support <perf_cap_>`_ and another is `Shared Memory Support
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<perf_cap_>`_. It can use :c:macro:`X86_FEATURE_CPPC` feature flag (for
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details refer to Processor Programming Reference (PPR) for AMD Family
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19h Model 51h, Revision A1 Processors [3]_) to indicate the different
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types. ``amd-pstate`` is to register different ``static_call`` instances
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for different hardware implementations.
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Currently, some of Zen2 and Zen3 processors support ``amd-pstate``. In the
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future, it will be supported on more and more AMD processors.
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Full MSR Support
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-----------------
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Some new Zen3 processors such as Cezanne provide the MSR registers directly
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while the :c:macro:`X86_FEATURE_CPPC` CPU feature flag is set.
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``amd-pstate`` can handle the MSR register to implement the fast switch
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function in ``CPUFreq`` that can shrink latency of frequency control on the
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interrupt context. The functions with ``pstate_xxx`` prefix represent the
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operations of MSR registers.
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Shared Memory Support
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----------------------
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If :c:macro:`X86_FEATURE_CPPC` CPU feature flag is not set, that means the
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processor supports shared memory solution. In this case, ``amd-pstate``
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uses the ``cppc_acpi`` helper methods to implement the callback functions
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that defined on ``static_call``. The functions with ``cppc_xxx`` prefix
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represent the operations of acpi cppc helpers for shared memory solution.
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AMD P-States and ACPI hardware P-States always can be supported in one
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processor. But AMD P-States has the higher priority and if it is enabled
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with :c:macro:`MSR_AMD_CPPC_ENABLE` or ``cppc_set_enable``, it will respond
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to the request from AMD P-States.
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User Space Interface in ``sysfs``
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==================================
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``amd-pstate`` exposes several global attributes (files) in ``sysfs`` to
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control its functionality at the system level. They located in the
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``/sys/devices/system/cpu/cpufreq/policyX/`` directory and affect all CPUs. ::
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root@hr-test1:/home/ray# ls /sys/devices/system/cpu/cpufreq/policy0/*amd*
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/sys/devices/system/cpu/cpufreq/policy0/amd_pstate_highest_perf
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/sys/devices/system/cpu/cpufreq/policy0/amd_pstate_lowest_nonlinear_freq
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/sys/devices/system/cpu/cpufreq/policy0/amd_pstate_max_freq
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``amd_pstate_highest_perf / amd_pstate_max_freq``
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Maximum CPPC performance and CPU frequency that the driver is allowed to
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set in percent of the maximum supported CPPC performance level (the highest
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performance supported in `AMD CPPC Performance Capability <perf_cap_>`_).
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In some of ASICs, the highest CPPC performance is not the one in the _CPC
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table, so we need to expose it to sysfs. If boost is not active but
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supported, this maximum frequency will be larger than the one in
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``cpuinfo``.
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This attribute is read-only.
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``amd_pstate_lowest_nonlinear_freq``
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The lowest non-linear CPPC CPU frequency that the driver is allowed to set
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in percent of the maximum supported CPPC performance level (Please see the
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lowest non-linear performance in `AMD CPPC Performance Capability
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<perf_cap_>`_).
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This attribute is read-only.
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For other performance and frequency values, we can read them back from
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``/sys/devices/system/cpu/cpuX/acpi_cppc/``, see :ref:`cppc_sysfs`.
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``amd-pstate`` vs ``acpi-cpufreq``
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======================================
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On majority of AMD platforms supported by ``acpi-cpufreq``, the ACPI tables
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provided by the platform firmware used for CPU performance scaling, but
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only provides 3 P-states on AMD processors.
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However, on modern AMD APU and CPU series, it provides the collaborative
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processor performance control according to ACPI protocol and customize this
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for AMD platforms. That is fine-grain and continuous frequency range
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instead of the legacy hardware P-states. ``amd-pstate`` is the kernel
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module which supports the new AMD P-States mechanism on most of future AMD
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platforms. The AMD P-States mechanism will be the more performance and energy
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efficiency frequency management method on AMD processors.
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Kernel Module Options for ``amd-pstate``
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=========================================
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``shared_mem``
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Use a module param (shared_mem) to enable related processors manually with
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**amd_pstate.shared_mem=1**.
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Due to the performance issue on the processors with `Shared Memory Support
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<perf_cap_>`_, so we disable it for the moment and will enable this by default
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once we address performance issue on this solution.
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The way to check whether current processor is `Full MSR Support <perf_cap_>`_
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or `Shared Memory Support <perf_cap_>`_ : ::
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ray@hr-test1:~$ lscpu | grep cppc
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Flags: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb rdtscp lm constant_tsc rep_good nopl nonstop_tsc cpuid extd_apicid aperfmperf rapl pni pclmulqdq monitor ssse3 fma cx16 sse4_1 sse4_2 x2apic movbe popcnt aes xsave avx f16c rdrand lahf_lm cmp_legacy svm extapic cr8_legacy abm sse4a misalignsse 3dnowprefetch osvw ibs skinit wdt tce topoext perfctr_core perfctr_nb bpext perfctr_llc mwaitx cpb cat_l3 cdp_l3 hw_pstate ssbd mba ibrs ibpb stibp vmmcall fsgsbase bmi1 avx2 smep bmi2 erms invpcid cqm rdt_a rdseed adx smap clflushopt clwb sha_ni xsaveopt xsavec xgetbv1 xsaves cqm_llc cqm_occup_llc cqm_mbm_total cqm_mbm_local clzero irperf xsaveerptr rdpru wbnoinvd cppc arat npt lbrv svm_lock nrip_save tsc_scale vmcb_clean flushbyasid decodeassists pausefilter pfthreshold avic v_vmsave_vmload vgif v_spec_ctrl umip pku ospke vaes vpclmulqdq rdpid overflow_recov succor smca fsrm
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If CPU Flags have cppc, then this processor supports `Full MSR Support
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<perf_cap_>`_. Otherwise it supports `Shared Memory Support <perf_cap_>`_.
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``cpupower`` tool support for ``amd-pstate``
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===============================================
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``amd-pstate`` is supported on ``cpupower`` tool that can be used to dump the frequency
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information. And it is in progress to support more and more operations for new
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``amd-pstate`` module with this tool. ::
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root@hr-test1:/home/ray# cpupower frequency-info
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analyzing CPU 0:
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driver: amd-pstate
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CPUs which run at the same hardware frequency: 0
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CPUs which need to have their frequency coordinated by software: 0
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maximum transition latency: 131 us
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hardware limits: 400 MHz - 4.68 GHz
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available cpufreq governors: ondemand conservative powersave userspace performance schedutil
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current policy: frequency should be within 400 MHz and 4.68 GHz.
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The governor "schedutil" may decide which speed to use
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within this range.
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current CPU frequency: Unable to call hardware
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current CPU frequency: 4.02 GHz (asserted by call to kernel)
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boost state support:
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Supported: yes
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Active: yes
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AMD PSTATE Highest Performance: 166. Maximum Frequency: 4.68 GHz.
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AMD PSTATE Nominal Performance: 117. Nominal Frequency: 3.30 GHz.
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AMD PSTATE Lowest Non-linear Performance: 39. Lowest Non-linear Frequency: 1.10 GHz.
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AMD PSTATE Lowest Performance: 15. Lowest Frequency: 400 MHz.
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Diagnostics and Tuning
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=======================
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Trace Events
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--------------
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There are two static trace events that can be used for ``amd-pstate``
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diagnostics. One of them is the cpu_frequency trace event generally used
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by ``CPUFreq``, and the other one is the ``amd_pstate_perf`` trace event
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specific to ``amd-pstate``. The following sequence of shell commands can
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be used to enable them and see their output (if the kernel is generally
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configured to support event tracing). ::
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root@hr-test1:/home/ray# cd /sys/kernel/tracing/
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root@hr-test1:/sys/kernel/tracing# echo 1 > events/amd_cpu/enable
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root@hr-test1:/sys/kernel/tracing# cat trace
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# tracer: nop
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#
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# entries-in-buffer/entries-written: 47827/42233061 #P:2
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#
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# _-----=> irqs-off
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# / _----=> need-resched
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# | / _---=> hardirq/softirq
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# || / _--=> preempt-depth
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# ||| / delay
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# TASK-PID CPU# |||| TIMESTAMP FUNCTION
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# | | | |||| | |
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<idle>-0 [015] dN... 4995.979886: amd_pstate_perf: amd_min_perf=85 amd_des_perf=85 amd_max_perf=166 cpu_id=15 changed=false fast_switch=true
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<idle>-0 [007] d.h.. 4995.979893: amd_pstate_perf: amd_min_perf=85 amd_des_perf=85 amd_max_perf=166 cpu_id=7 changed=false fast_switch=true
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cat-2161 [000] d.... 4995.980841: amd_pstate_perf: amd_min_perf=85 amd_des_perf=85 amd_max_perf=166 cpu_id=0 changed=false fast_switch=true
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sshd-2125 [004] d.s.. 4995.980968: amd_pstate_perf: amd_min_perf=85 amd_des_perf=85 amd_max_perf=166 cpu_id=4 changed=false fast_switch=true
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<idle>-0 [007] d.s.. 4995.980968: amd_pstate_perf: amd_min_perf=85 amd_des_perf=85 amd_max_perf=166 cpu_id=7 changed=false fast_switch=true
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<idle>-0 [003] d.s.. 4995.980971: amd_pstate_perf: amd_min_perf=85 amd_des_perf=85 amd_max_perf=166 cpu_id=3 changed=false fast_switch=true
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<idle>-0 [011] d.s.. 4995.980996: amd_pstate_perf: amd_min_perf=85 amd_des_perf=85 amd_max_perf=166 cpu_id=11 changed=false fast_switch=true
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The cpu_frequency trace event will be triggered either by the ``schedutil`` scaling
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governor (for the policies it is attached to), or by the ``CPUFreq`` core (for the
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policies with other scaling governors).
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Reference
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===========
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.. [1] AMD64 Architecture Programmer's Manual Volume 2: System Programming,
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https://www.amd.com/system/files/TechDocs/24593.pdf
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.. [2] Advanced Configuration and Power Interface Specification,
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https://uefi.org/sites/default/files/resources/ACPI_Spec_6_4_Jan22.pdf
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.. [3] Processor Programming Reference (PPR) for AMD Family 19h Model 51h, Revision A1 Processors
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https://www.amd.com/system/files/TechDocs/56569-A1-PUB.zip
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