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baf172cc04
The new SM8550 SoC bumps up the HW version of QMP phy to v6.20 for PCIE g4x2. Add the new PCS PCIE specific offsets in a dedicated header file. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20230208180020.2761766-6-abel.vesa@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
23 lines
863 B
C
23 lines
863 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2023, Linaro Limited
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*/
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#ifndef QCOM_PHY_QMP_PCS_PCIE_V6_20_H_
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#define QCOM_PHY_QMP_PCS_PCIE_V6_20_H_
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/* Only for QMP V6_20 PHY - PCIE have different offsets than V5 */
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#define QPHY_PCIE_V6_20_PCS_POWER_STATE_CONFIG2 0x00c
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#define QPHY_PCIE_V6_20_PCS_TX_RX_CONFIG 0x018
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#define QPHY_PCIE_V6_20_PCS_ENDPOINT_REFCLK_DRIVE 0x01c
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#define QPHY_PCIE_V6_20_PCS_OSC_DTCT_ATCIONS 0x090
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#define QPHY_PCIE_V6_20_PCS_EQ_CONFIG1 0x0a0
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#define QPHY_PCIE_V6_20_PCS_EQ_CONFIG5 0x108
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#define QPHY_PCIE_V6_20_PCS_G4_PRE_GAIN 0x15c
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#define QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG1 0x17c
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#define QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG3 0x184
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#define QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG5 0x18c
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#define QPHY_PCIE_V6_20_PCS_G3_FOM_EQ_CONFIG5 0x1ac
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#define QPHY_PCIE_V6_20_PCS_G4_FOM_EQ_CONFIG5 0x1c0
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#endif
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