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dc55a1231e
The new SM8550 SoC bumps up the HW version of QMP phy to v6. Add the new DP specific offsets in the generic qmp header file. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230208183421.2874423-6-abel.vesa@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
141 lines
4.6 KiB
C
141 lines
4.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2017, The Linux Foundation. All rights reserved.
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*/
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#ifndef QCOM_PHY_QMP_H_
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#define QCOM_PHY_QMP_H_
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#include "phy-qcom-qmp-qserdes-com.h"
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#include "phy-qcom-qmp-qserdes-txrx.h"
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#include "phy-qcom-qmp-qserdes-com-v3.h"
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#include "phy-qcom-qmp-qserdes-txrx-v3.h"
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#include "phy-qcom-qmp-qserdes-com-v4.h"
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#include "phy-qcom-qmp-qserdes-txrx-v4.h"
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#include "phy-qcom-qmp-qserdes-txrx-v4_20.h"
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#include "phy-qcom-qmp-qserdes-com-v5.h"
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#include "phy-qcom-qmp-qserdes-txrx-v5.h"
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#include "phy-qcom-qmp-qserdes-txrx-v5_20.h"
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#include "phy-qcom-qmp-qserdes-txrx-v5_5nm.h"
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#include "phy-qcom-qmp-qserdes-com-v6.h"
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#include "phy-qcom-qmp-qserdes-txrx-v6.h"
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#include "phy-qcom-qmp-qserdes-txrx-v6_20.h"
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#include "phy-qcom-qmp-qserdes-ln-shrd-v6.h"
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#include "phy-qcom-qmp-qserdes-pll.h"
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#include "phy-qcom-qmp-pcs-v2.h"
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#include "phy-qcom-qmp-pcs-v3.h"
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#include "phy-qcom-qmp-pcs-v4.h"
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#include "phy-qcom-qmp-pcs-v4_20.h"
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#include "phy-qcom-qmp-pcs-v5.h"
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#include "phy-qcom-qmp-pcs-v5_20.h"
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#include "phy-qcom-qmp-pcs-v6.h"
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#include "phy-qcom-qmp-pcs-v6_20.h"
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/* Only for QMP V3 & V4 PHY - DP COM registers */
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#define QPHY_V3_DP_COM_PHY_MODE_CTRL 0x00
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#define QPHY_V3_DP_COM_SW_RESET 0x04
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#define QPHY_V3_DP_COM_POWER_DOWN_CTRL 0x08
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#define QPHY_V3_DP_COM_SWI_CTRL 0x0c
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#define QPHY_V3_DP_COM_TYPEC_CTRL 0x10
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#define QPHY_V3_DP_COM_TYPEC_PWRDN_CTRL 0x14
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#define QPHY_V3_DP_COM_RESET_OVRD_CTRL 0x1c
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/* QSERDES V3 COM bits */
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# define QSERDES_V3_COM_BIAS_EN 0x0001
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# define QSERDES_V3_COM_BIAS_EN_MUX 0x0002
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# define QSERDES_V3_COM_CLKBUF_R_EN 0x0004
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# define QSERDES_V3_COM_CLKBUF_L_EN 0x0008
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# define QSERDES_V3_COM_EN_SYSCLK_TX_SEL 0x0010
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# define QSERDES_V3_COM_CLKBUF_RX_DRIVE_L 0x0020
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# define QSERDES_V3_COM_CLKBUF_RX_DRIVE_R 0x0040
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/* QSERDES V3 TX bits */
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# define DP_PHY_TXn_TX_EMP_POST1_LVL_MASK 0x001f
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# define DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN 0x0020
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# define DP_PHY_TXn_TX_DRV_LVL_MASK 0x001f
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# define DP_PHY_TXn_TX_DRV_LVL_MUX_EN 0x0020
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/* QMP PHY - DP PHY registers */
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#define QSERDES_DP_PHY_REVISION_ID0 0x000
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#define QSERDES_DP_PHY_REVISION_ID1 0x004
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#define QSERDES_DP_PHY_REVISION_ID2 0x008
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#define QSERDES_DP_PHY_REVISION_ID3 0x00c
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#define QSERDES_DP_PHY_CFG 0x010
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#define QSERDES_DP_PHY_PD_CTL 0x018
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# define DP_PHY_PD_CTL_PWRDN 0x001
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# define DP_PHY_PD_CTL_PSR_PWRDN 0x002
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# define DP_PHY_PD_CTL_AUX_PWRDN 0x004
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# define DP_PHY_PD_CTL_LANE_0_1_PWRDN 0x008
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# define DP_PHY_PD_CTL_LANE_2_3_PWRDN 0x010
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# define DP_PHY_PD_CTL_PLL_PWRDN 0x020
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# define DP_PHY_PD_CTL_DP_CLAMP_EN 0x040
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#define QSERDES_DP_PHY_MODE 0x01c
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#define QSERDES_DP_PHY_AUX_CFG0 0x020
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#define QSERDES_DP_PHY_AUX_CFG1 0x024
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#define QSERDES_DP_PHY_AUX_CFG2 0x028
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#define QSERDES_DP_PHY_AUX_CFG3 0x02c
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#define QSERDES_DP_PHY_AUX_CFG4 0x030
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#define QSERDES_DP_PHY_AUX_CFG5 0x034
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#define QSERDES_DP_PHY_AUX_CFG6 0x038
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#define QSERDES_DP_PHY_AUX_CFG7 0x03c
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#define QSERDES_DP_PHY_AUX_CFG8 0x040
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#define QSERDES_DP_PHY_AUX_CFG9 0x044
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/* Only for QMP V3 PHY - DP PHY registers */
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#define QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK 0x048
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# define PHY_AUX_STOP_ERR_MASK 0x01
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# define PHY_AUX_DEC_ERR_MASK 0x02
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# define PHY_AUX_SYNC_ERR_MASK 0x04
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# define PHY_AUX_ALIGN_ERR_MASK 0x08
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# define PHY_AUX_REQ_ERR_MASK 0x10
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#define QSERDES_V3_DP_PHY_AUX_INTERRUPT_CLEAR 0x04c
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#define QSERDES_V3_DP_PHY_AUX_BIST_CFG 0x050
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#define QSERDES_V3_DP_PHY_VCO_DIV 0x064
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#define QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL 0x06c
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#define QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL 0x088
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#define QSERDES_V3_DP_PHY_SPARE0 0x0ac
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#define DP_PHY_SPARE0_MASK 0x0f
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#define DP_PHY_SPARE0_ORIENTATION_INFO_SHIFT 0x04(0x0004)
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#define QSERDES_V3_DP_PHY_STATUS 0x0c0
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/* Only for QMP V4 PHY - DP PHY registers */
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#define QSERDES_V4_DP_PHY_CFG_1 0x014
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#define QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK 0x054
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#define QSERDES_V4_DP_PHY_AUX_INTERRUPT_CLEAR 0x058
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#define QSERDES_V4_DP_PHY_VCO_DIV 0x070
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#define QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL 0x078
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#define QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL 0x09c
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#define QSERDES_V4_DP_PHY_SPARE0 0x0c8
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#define QSERDES_V4_DP_PHY_AUX_INTERRUPT_STATUS 0x0d8
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#define QSERDES_V4_DP_PHY_STATUS 0x0dc
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/* Only for QMP V4 PHY - PCS_MISC registers */
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#define QPHY_V4_PCS_MISC_TYPEC_CTRL 0x00
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#define QPHY_V4_PCS_MISC_TYPEC_PWRDN_CTRL 0x04
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#define QPHY_V4_PCS_MISC_PCS_MISC_CONFIG1 0x08
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#define QPHY_V4_PCS_MISC_CLAMP_ENABLE 0x0c
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#define QPHY_V4_PCS_MISC_TYPEC_STATUS 0x10
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#define QPHY_V4_PCS_MISC_PLACEHOLDER_STATUS 0x14
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/* Only for QMP V6 PHY - DP PHY registers */
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#define QSERDES_V6_DP_PHY_AUX_INTERRUPT_STATUS 0x0e0
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#define QSERDES_V6_DP_PHY_STATUS 0x0e4
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#endif
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