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![Linus Torvalds](/assets/img/avatar_default.png)
Small Things: - Move OpenRISC docs into Documentation and clean them up - Document previously undocumented devicetree bindings - Update the or1ksim dts to use stdout-path OpenRISC SMP support details: - First the "use shadow registers" and "define CPU_BIG_ENDIAN as true" get the architecture ready for SMP. - The "add 1 and 2 byte cmpxchg support" and "use qspinlocks and qrwlocks" add the SMP locking infrastructure as needed. Using the qspinlocks and qrwlocks as suggested by Peter Z while reviewing the original spinlocks implementation. - The "support for ompic" adds a new irqchip device which is used for IPI communication to support SMP. - The "initial SMP support" adds smp.c and makes changes to all of the necessary data-structures to be per-cpu. - The remaining patches are bug fixes and debug helpers which I wanted to keep separate from the "initial SMP support" in order to allow them to be reviewed on their own. This includes: - add cacheflush support to fix icache aliasing - fix initial preempt state for secondary cpu tasks - sleep instead of spin on secondary wait - support framepointers and STACKTRACE_SUPPORT - enable LOCKDEP_SUPPORT and irqflags tracing - timer sync: Add tick timer sync logic - fix possible deadlock in timer sync, pointed out by mips guys Note: the irqchip patch was reviewed with Marc and we agreed to push it together with these patches. -----BEGIN PGP SIGNATURE----- iQIcBAABAgAGBQJaCaO/AAoJEMOzHC1eZifkwyUQAIwp5q242D5P0Mo8gvpmNZ7s Lc7XBe1+dahbW8OIh0b8XhufkwFHY614bnrDBAr8GOcbaOXgxk8LbhTmkwbFO9z7 fm5YKr7il0dunCWfw278sQcZsCRQ9sQkXIei0gJL/56Uq6dbJhIREcOgjHBjDW5r tblrbv70fPmTCP/7cw08y4QwXIAf+8zEhECJcDKqFZ2nhQkWQUd3BAppxdCOWSDa aV9qOa/koP9lAKg8aWOCwCuS+WK386KNCCowsTxpyWdl9tMWsebeBh1odxteKiiB KpAENfEvbjuYMWH3CQ+XdSDDdIdGnIP6l5KDzBkhF1USXwS7AlaMUpbPHcLXVRFi 1S2zcO9i6WfTnaDpNZc+L8oHqgyLUDJ6RgC6juLEmbfnCVmzNkLKCYa3d3JRI/oC 6qxpHYkLKWsJoOHDcs0fiMOLhkJZrzPYkIv0fW+uwTM10onxhm48fm6RNWuwqXWd 4FoH8ufqeACxWEotv6pcL7RUYrmX1gmvxby8CCHiUBIBoRM3bGmqTVvgX64nULgB QIn/74R3J6GDPKicHDcq8ZOnMWvE6nbpXXbX73PqjXMf80HVjejV3Fg2su8m7LR0 +ni1ndKYB3V+t0+m1m5eMvpKMQ2HrMIMdx0M4xL+Z0fT8B3lcZWpb4wBsG7E+C49 pyf9xEk34Fe7HR+7KBO9 =euP7 -----END PGP SIGNATURE----- Merge tag 'for-linus' of git://github.com/openrisc/linux Pull OpenRISC updates from Stafford Horne: "The OpenRISC work is a bit more interesting this time, adding SMP support and a few general cleanups. Small Things: - Move OpenRISC docs into Documentation and clean them up - Document previously undocumented devicetree bindings - Update the or1ksim dts to use stdout-path OpenRISC SMP support details: - First the "use shadow registers" and "define CPU_BIG_ENDIAN as true" get the architecture ready for SMP. - The "add 1 and 2 byte cmpxchg support" and "use qspinlocks and qrwlocks" add the SMP locking infrastructure as needed. Using the qspinlocks and qrwlocks as suggested by Peter Z while reviewing the original spinlocks implementation. - The "support for ompic" adds a new irqchip device which is used for IPI communication to support SMP. - The "initial SMP support" adds smp.c and makes changes to all of the necessary data-structures to be per-cpu. The remaining patches are bug fixes and debug helpers which I wanted to keep separate from the "initial SMP support" in order to allow them to be reviewed on their own. This includes: - add cacheflush support to fix icache aliasing - fix initial preempt state for secondary cpu tasks - sleep instead of spin on secondary wait - support framepointers and STACKTRACE_SUPPORT - enable LOCKDEP_SUPPORT and irqflags tracing - timer sync: Add tick timer sync logic - fix possible deadlock in timer sync, pointed out by mips guys Note: the irqchip patch was reviewed with Marc and we agreed to push it together with these patches" * tag 'for-linus' of git://github.com/openrisc/linux: openrisc: fix possible deadlock scenario during timer sync openrisc: pass endianness info to sparse openrisc: add tick timer multi-core sync logic openrisc: enable LOCKDEP_SUPPORT and irqflags tracing openrisc: support framepointers and STACKTRACE_SUPPORT openrisc: add simple_smp dts and defconfig for simulators openrisc: add cacheflush support to fix icache aliasing openrisc: sleep instead of spin on secondary wait openrisc: fix initial preempt state for secondary cpu tasks openrisc: initial SMP support irqchip: add initial support for ompic dt-bindings: add openrisc to vendor prefixes list openrisc: use qspinlocks and qrwlocks openrisc: add 1 and 2 byte cmpxchg support openrisc: use shadow registers to save regs on exception dt-bindings: openrisc: Add OpenRISC platform SoC Documentation: openrisc: Updates to README Documentation: Move OpenRISC docs out of arch/ MAINTAINERS: Add OpenRISC pic maintainer openrisc: dts: or1ksim: Add stdout-path
56 lines
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56 lines
1 KiB
Text
// SPDX-License-Identifier: GPL-2.0
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/dts-v1/;
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/ {
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compatible = "opencores,or1ksim";
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&pic>;
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aliases {
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uart0 = &serial0;
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};
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chosen {
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bootargs = "earlycon";
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stdout-path = "uart0:115200";
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};
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memory@0 {
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device_type = "memory";
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reg = <0x00000000 0x02000000>;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "opencores,or1200-rtlsvn481";
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reg = <0>;
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clock-frequency = <20000000>;
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};
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};
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/*
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* OR1K PIC is built into CPU and accessed via special purpose
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* registers. It is not addressable and, hence, has no 'reg'
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* property.
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*/
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pic: pic {
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compatible = "opencores,or1k-pic";
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#interrupt-cells = <1>;
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interrupt-controller;
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};
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serial0: serial@90000000 {
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compatible = "opencores,uart16550-rtlsvn105", "ns16550a";
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reg = <0x90000000 0x100>;
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interrupts = <2>;
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clock-frequency = <20000000>;
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};
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enet0: ethoc@92000000 {
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compatible = "opencores,ethmac-rtlsvn338";
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reg = <0x92000000 0x100>;
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interrupts = <4>;
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};
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};
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