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8799ee9f49
On some CPUs, bit 4 of section mappings means "update the cache when written to". On others, this bit is required to be one, and others it's required to be zero. Finally, on ARMv6 and above, setting it turns on "no execute" and prevents speculative prefetches. With all these combinations, no one value fits all CPUs, so we have to pick a value depending on the CPU type, and the area we're mapping. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
90 lines
2.5 KiB
C
90 lines
2.5 KiB
C
/*
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* linux/include/asm-arm/pgtable-hwdef.h
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*
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* Copyright (C) 1995-2002 Russell King
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef _ASMARM_PGTABLE_HWDEF_H
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#define _ASMARM_PGTABLE_HWDEF_H
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/*
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* Hardware page table definitions.
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*
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* + Level 1 descriptor (PMD)
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* - common
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*/
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#define PMD_TYPE_MASK (3 << 0)
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#define PMD_TYPE_FAULT (0 << 0)
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#define PMD_TYPE_TABLE (1 << 0)
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#define PMD_TYPE_SECT (2 << 0)
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#define PMD_BIT4 (1 << 4)
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#define PMD_DOMAIN(x) ((x) << 5)
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#define PMD_PROTECTION (1 << 9) /* v5 */
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/*
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* - section
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*/
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#define PMD_SECT_BUFFERABLE (1 << 2)
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#define PMD_SECT_CACHEABLE (1 << 3)
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#define PMD_SECT_XN (1 << 4) /* v6 */
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#define PMD_SECT_AP_WRITE (1 << 10)
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#define PMD_SECT_AP_READ (1 << 11)
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#define PMD_SECT_TEX(x) ((x) << 12) /* v5 */
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#define PMD_SECT_APX (1 << 15) /* v6 */
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#define PMD_SECT_S (1 << 16) /* v6 */
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#define PMD_SECT_nG (1 << 17) /* v6 */
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#define PMD_SECT_SUPER (1 << 18) /* v6 */
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#define PMD_SECT_UNCACHED (0)
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#define PMD_SECT_BUFFERED (PMD_SECT_BUFFERABLE)
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#define PMD_SECT_WT (PMD_SECT_CACHEABLE)
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#define PMD_SECT_WB (PMD_SECT_CACHEABLE | PMD_SECT_BUFFERABLE)
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#define PMD_SECT_MINICACHE (PMD_SECT_TEX(1) | PMD_SECT_CACHEABLE)
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#define PMD_SECT_WBWA (PMD_SECT_TEX(1) | PMD_SECT_CACHEABLE | PMD_SECT_BUFFERABLE)
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#define PMD_SECT_NONSHARED_DEV (PMD_SECT_TEX(2))
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/*
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* - coarse table (not used)
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*/
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/*
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* + Level 2 descriptor (PTE)
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* - common
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*/
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#define PTE_TYPE_MASK (3 << 0)
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#define PTE_TYPE_FAULT (0 << 0)
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#define PTE_TYPE_LARGE (1 << 0)
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#define PTE_TYPE_SMALL (2 << 0)
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#define PTE_TYPE_EXT (3 << 0) /* v5 */
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#define PTE_BUFFERABLE (1 << 2)
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#define PTE_CACHEABLE (1 << 3)
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/*
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* - extended small page/tiny page
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*/
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#define PTE_EXT_XN (1 << 0) /* v6 */
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#define PTE_EXT_AP_MASK (3 << 4)
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#define PTE_EXT_AP0 (1 << 4)
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#define PTE_EXT_AP1 (2 << 4)
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#define PTE_EXT_AP_UNO_SRO (0 << 4)
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#define PTE_EXT_AP_UNO_SRW (PTE_EXT_AP0)
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#define PTE_EXT_AP_URO_SRW (PTE_EXT_AP1)
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#define PTE_EXT_AP_URW_SRW (PTE_EXT_AP1|PTE_EXT_AP0)
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#define PTE_EXT_TEX(x) ((x) << 6) /* v5 */
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#define PTE_EXT_APX (1 << 9) /* v6 */
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#define PTE_EXT_COHERENT (1 << 9) /* XScale3 */
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#define PTE_EXT_SHARED (1 << 10) /* v6 */
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#define PTE_EXT_NG (1 << 11) /* v6 */
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/*
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* - small page
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*/
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#define PTE_SMALL_AP_MASK (0xff << 4)
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#define PTE_SMALL_AP_UNO_SRO (0x00 << 4)
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#define PTE_SMALL_AP_UNO_SRW (0x55 << 4)
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#define PTE_SMALL_AP_URO_SRW (0xaa << 4)
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#define PTE_SMALL_AP_URW_SRW (0xff << 4)
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#endif
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