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To avoid future mistakes in the device tree for the clockgen module, add constants for the clockgen subtype as well as a macro for the PLL divider. Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20201108185113.31377-4-michael@walle.cc Signed-off-by: Stephen Boyd <sboyd@kernel.org>
15 lines
374 B
C
15 lines
374 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef DT_CLOCK_FSL_QORIQ_CLOCKGEN_H
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#define DT_CLOCK_FSL_QORIQ_CLOCKGEN_H
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#define QORIQ_CLK_SYSCLK 0
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#define QORIQ_CLK_CMUX 1
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#define QORIQ_CLK_HWACCEL 2
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#define QORIQ_CLK_FMAN 3
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#define QORIQ_CLK_PLATFORM_PLL 4
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#define QORIQ_CLK_CORECLK 5
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#define QORIQ_CLK_PLL_DIV(x) ((x) - 1)
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#endif /* DT_CLOCK_FSL_QORIQ_CLOCKGEN_H */
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