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133bb341b9
When submitted v2 of the G12A AO-CLK IDs, the CLKID_AO_CTS_OSCIN was moved
to the internal non-exported bindings, but this clock is necessary for
the second AO-CEC-B module since it embeds the 32768Hz dual-divider
clock generator unlike the AO-CEC-A module.
Export it back to the public bindings.
Fixes: be3d960b0a ("dt-bindings: clk: add G12A AO Clock and Reset Bindings")
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lkml.kernel.org/r/20190321092010.14382-1-narmstrong@baylibre.com
36 lines
956 B
C
36 lines
956 B
C
/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
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/*
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* Copyright (c) 2016 BayLibre, SAS
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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*
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* Copyright (c) 2018 Amlogic, inc.
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* Author: Qiufang Dai <qiufang.dai@amlogic.com>
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*/
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#ifndef DT_BINDINGS_CLOCK_AMLOGIC_MESON_G12A_AOCLK
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#define DT_BINDINGS_CLOCK_AMLOGIC_MESON_G12A_AOCLK
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#define CLKID_AO_AHB 0
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#define CLKID_AO_IR_IN 1
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#define CLKID_AO_I2C_M0 2
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#define CLKID_AO_I2C_S0 3
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#define CLKID_AO_UART 4
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#define CLKID_AO_PROD_I2C 5
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#define CLKID_AO_UART2 6
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#define CLKID_AO_IR_OUT 7
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#define CLKID_AO_SAR_ADC 8
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#define CLKID_AO_MAILBOX 9
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#define CLKID_AO_M3 10
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#define CLKID_AO_AHB_SRAM 11
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#define CLKID_AO_RTI 12
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#define CLKID_AO_M4_FCLK 13
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#define CLKID_AO_M4_HCLK 14
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#define CLKID_AO_CLK81 15
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#define CLKID_AO_SAR_ADC_SEL 16
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#define CLKID_AO_SAR_ADC_CLK 18
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#define CLKID_AO_CTS_OSCIN 19
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#define CLKID_AO_32K 23
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#define CLKID_AO_CEC 27
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#define CLKID_AO_CTS_RTC_OSCIN 28
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#endif
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