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bd08b193cf
stm32mp15 TZ secure firmware provides SCMI clocks for oscillators, some PLL output and few secure aware interfaces. This change defines the SCMI clock identifiers used by SCMI agents and servers. Server SCMI0 exposes clocks and reset controllers for resources under RCC[TZEN] configuration control. Server SCMI1 exposes clocks for resources under RCC[MCKPROT] control. Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com> Acked-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20210617051814.12018-8-gabriel.fernandez@foss.st.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
278 lines
5.2 KiB
C
278 lines
5.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */
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/*
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* Copyright (C) STMicroelectronics 2018 - All Rights Reserved
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* Author: Gabriel Fernandez <gabriel.fernandez@st.com> for STMicroelectronics.
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*/
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#ifndef _DT_BINDINGS_STM32MP1_CLKS_H_
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#define _DT_BINDINGS_STM32MP1_CLKS_H_
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/* OSCILLATOR clocks */
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#define CK_HSE 0
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#define CK_CSI 1
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#define CK_LSI 2
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#define CK_LSE 3
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#define CK_HSI 4
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#define CK_HSE_DIV2 5
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/* Bus clocks */
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#define TIM2 6
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#define TIM3 7
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#define TIM4 8
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#define TIM5 9
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#define TIM6 10
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#define TIM7 11
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#define TIM12 12
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#define TIM13 13
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#define TIM14 14
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#define LPTIM1 15
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#define SPI2 16
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#define SPI3 17
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#define USART2 18
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#define USART3 19
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#define UART4 20
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#define UART5 21
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#define UART7 22
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#define UART8 23
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#define I2C1 24
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#define I2C2 25
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#define I2C3 26
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#define I2C5 27
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#define SPDIF 28
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#define CEC 29
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#define DAC12 30
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#define MDIO 31
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#define TIM1 32
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#define TIM8 33
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#define TIM15 34
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#define TIM16 35
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#define TIM17 36
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#define SPI1 37
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#define SPI4 38
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#define SPI5 39
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#define USART6 40
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#define SAI1 41
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#define SAI2 42
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#define SAI3 43
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#define DFSDM 44
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#define FDCAN 45
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#define LPTIM2 46
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#define LPTIM3 47
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#define LPTIM4 48
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#define LPTIM5 49
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#define SAI4 50
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#define SYSCFG 51
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#define VREF 52
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#define TMPSENS 53
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#define PMBCTRL 54
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#define HDP 55
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#define LTDC 56
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#define DSI 57
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#define IWDG2 58
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#define USBPHY 59
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#define STGENRO 60
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#define SPI6 61
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#define I2C4 62
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#define I2C6 63
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#define USART1 64
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#define RTCAPB 65
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#define TZC1 66
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#define TZPC 67
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#define IWDG1 68
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#define BSEC 69
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#define STGEN 70
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#define DMA1 71
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#define DMA2 72
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#define DMAMUX 73
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#define ADC12 74
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#define USBO 75
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#define SDMMC3 76
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#define DCMI 77
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#define CRYP2 78
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#define HASH2 79
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#define RNG2 80
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#define CRC2 81
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#define HSEM 82
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#define IPCC 83
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#define GPIOA 84
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#define GPIOB 85
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#define GPIOC 86
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#define GPIOD 87
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#define GPIOE 88
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#define GPIOF 89
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#define GPIOG 90
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#define GPIOH 91
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#define GPIOI 92
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#define GPIOJ 93
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#define GPIOK 94
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#define GPIOZ 95
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#define CRYP1 96
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#define HASH1 97
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#define RNG1 98
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#define BKPSRAM 99
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#define MDMA 100
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#define GPU 101
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#define ETHCK 102
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#define ETHTX 103
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#define ETHRX 104
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#define ETHMAC 105
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#define FMC 106
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#define QSPI 107
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#define SDMMC1 108
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#define SDMMC2 109
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#define CRC1 110
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#define USBH 111
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#define ETHSTP 112
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#define TZC2 113
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/* Kernel clocks */
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#define SDMMC1_K 118
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#define SDMMC2_K 119
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#define SDMMC3_K 120
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#define FMC_K 121
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#define QSPI_K 122
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#define ETHCK_K 123
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#define RNG1_K 124
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#define RNG2_K 125
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#define GPU_K 126
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#define USBPHY_K 127
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#define STGEN_K 128
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#define SPDIF_K 129
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#define SPI1_K 130
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#define SPI2_K 131
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#define SPI3_K 132
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#define SPI4_K 133
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#define SPI5_K 134
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#define SPI6_K 135
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#define CEC_K 136
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#define I2C1_K 137
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#define I2C2_K 138
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#define I2C3_K 139
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#define I2C4_K 140
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#define I2C5_K 141
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#define I2C6_K 142
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#define LPTIM1_K 143
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#define LPTIM2_K 144
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#define LPTIM3_K 145
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#define LPTIM4_K 146
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#define LPTIM5_K 147
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#define USART1_K 148
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#define USART2_K 149
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#define USART3_K 150
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#define UART4_K 151
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#define UART5_K 152
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#define USART6_K 153
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#define UART7_K 154
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#define UART8_K 155
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#define DFSDM_K 156
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#define FDCAN_K 157
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#define SAI1_K 158
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#define SAI2_K 159
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#define SAI3_K 160
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#define SAI4_K 161
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#define ADC12_K 162
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#define DSI_K 163
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#define DSI_PX 164
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#define ADFSDM_K 165
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#define USBO_K 166
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#define LTDC_PX 167
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#define DAC12_K 168
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#define ETHPTP_K 169
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/* PLL */
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#define PLL1 176
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#define PLL2 177
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#define PLL3 178
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#define PLL4 179
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/* ODF */
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#define PLL1_P 180
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#define PLL1_Q 181
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#define PLL1_R 182
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#define PLL2_P 183
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#define PLL2_Q 184
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#define PLL2_R 185
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#define PLL3_P 186
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#define PLL3_Q 187
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#define PLL3_R 188
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#define PLL4_P 189
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#define PLL4_Q 190
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#define PLL4_R 191
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/* AUX */
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#define RTC 192
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/* MCLK */
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#define CK_PER 193
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#define CK_MPU 194
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#define CK_AXI 195
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#define CK_MCU 196
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/* Time base */
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#define TIM2_K 197
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#define TIM3_K 198
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#define TIM4_K 199
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#define TIM5_K 200
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#define TIM6_K 201
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#define TIM7_K 202
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#define TIM12_K 203
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#define TIM13_K 204
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#define TIM14_K 205
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#define TIM1_K 206
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#define TIM8_K 207
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#define TIM15_K 208
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#define TIM16_K 209
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#define TIM17_K 210
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/* MCO clocks */
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#define CK_MCO1 211
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#define CK_MCO2 212
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/* TRACE & DEBUG clocks */
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#define CK_DBG 214
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#define CK_TRACE 215
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/* DDR */
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#define DDRC1 220
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#define DDRC1LP 221
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#define DDRC2 222
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#define DDRC2LP 223
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#define DDRPHYC 224
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#define DDRPHYCLP 225
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#define DDRCAPB 226
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#define DDRCAPBLP 227
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#define AXIDCG 228
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#define DDRPHYCAPB 229
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#define DDRPHYCAPBLP 230
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#define DDRPERFM 231
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#define STM32MP1_LAST_CLK 232
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/* SCMI clock identifiers */
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#define CK_SCMI0_HSE 0
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#define CK_SCMI0_HSI 1
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#define CK_SCMI0_CSI 2
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#define CK_SCMI0_LSE 3
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#define CK_SCMI0_LSI 4
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#define CK_SCMI0_PLL2_Q 5
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#define CK_SCMI0_PLL2_R 6
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#define CK_SCMI0_MPU 7
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#define CK_SCMI0_AXI 8
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#define CK_SCMI0_BSEC 9
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#define CK_SCMI0_CRYP1 10
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#define CK_SCMI0_GPIOZ 11
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#define CK_SCMI0_HASH1 12
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#define CK_SCMI0_I2C4 13
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#define CK_SCMI0_I2C6 14
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#define CK_SCMI0_IWDG1 15
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#define CK_SCMI0_RNG1 16
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#define CK_SCMI0_RTC 17
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#define CK_SCMI0_RTCAPB 18
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#define CK_SCMI0_SPI6 19
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#define CK_SCMI0_USART1 20
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#define CK_SCMI1_PLL3_Q 0
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#define CK_SCMI1_PLL3_R 1
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#define CK_SCMI1_MCU 2
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#endif /* _DT_BINDINGS_STM32MP1_CLKS_H_ */
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