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c962f10f39
The D1 has a CCU and a R_CCU (PRCM CCU) like most other sunxi SoCs, with 3 and 4 clock inputs, respectively. Add the compatibles and bindings. Signed-off-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20211119043545.4010-2-samuel@sholland.org
19 lines
456 B
C
19 lines
456 B
C
/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
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/*
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* Copyright (C) 2021 Samuel Holland <samuel@sholland.org>
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*/
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#ifndef _DT_BINDINGS_CLK_SUN20I_D1_R_CCU_H_
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#define _DT_BINDINGS_CLK_SUN20I_D1_R_CCU_H_
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#define CLK_R_AHB 0
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#define CLK_BUS_R_TIMER 2
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#define CLK_BUS_R_TWD 3
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#define CLK_BUS_R_PPU 4
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#define CLK_R_IR_RX 5
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#define CLK_BUS_R_IR_RX 6
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#define CLK_BUS_R_RTC 7
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#define CLK_BUS_R_CPUCFG 8
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#endif /* _DT_BINDINGS_CLK_SUN20I_D1_R_CCU_H_ */
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