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65abc8ef57
According to Tegra X1 TRM, there are missing swgroups in the tegra210_swgroups list. So this patch adds them in bindings. Note that the TEGRA_SWGROUP_GPU (in list) should be actually TEGRA_SWGROUP_GPUB (in TRM), yet TEGRA_SWGROUP_GPU (in TRM) is not being used -- only TEGRA_SWGROUP_GPUB (in TRM) is. So this patch does not add TEGRA_SWGROUP_GPU (in TRM) and keeps TEGRA_SWGROUP_GPU (in list) as it is. Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com> Acked-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20201008003746.25659-5-nicoleotsuka@gmail.com Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
78 lines
2.4 KiB
C
78 lines
2.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef DT_BINDINGS_MEMORY_TEGRA210_MC_H
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#define DT_BINDINGS_MEMORY_TEGRA210_MC_H
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#define TEGRA_SWGROUP_PTC 0
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#define TEGRA_SWGROUP_DC 1
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#define TEGRA_SWGROUP_DCB 2
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#define TEGRA_SWGROUP_AFI 3
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#define TEGRA_SWGROUP_AVPC 4
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#define TEGRA_SWGROUP_HDA 5
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#define TEGRA_SWGROUP_HC 6
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#define TEGRA_SWGROUP_NVENC 7
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#define TEGRA_SWGROUP_PPCS 8
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#define TEGRA_SWGROUP_SATA 9
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#define TEGRA_SWGROUP_MPCORE 10
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#define TEGRA_SWGROUP_ISP2 11
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#define TEGRA_SWGROUP_XUSB_HOST 12
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#define TEGRA_SWGROUP_XUSB_DEV 13
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#define TEGRA_SWGROUP_ISP2B 14
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#define TEGRA_SWGROUP_TSEC 15
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#define TEGRA_SWGROUP_A9AVP 16
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#define TEGRA_SWGROUP_GPU 17
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#define TEGRA_SWGROUP_SDMMC1A 18
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#define TEGRA_SWGROUP_SDMMC2A 19
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#define TEGRA_SWGROUP_SDMMC3A 20
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#define TEGRA_SWGROUP_SDMMC4A 21
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#define TEGRA_SWGROUP_VIC 22
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#define TEGRA_SWGROUP_VI 23
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#define TEGRA_SWGROUP_NVDEC 24
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#define TEGRA_SWGROUP_APE 25
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#define TEGRA_SWGROUP_NVJPG 26
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#define TEGRA_SWGROUP_SE 27
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#define TEGRA_SWGROUP_AXIAP 28
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#define TEGRA_SWGROUP_ETR 29
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#define TEGRA_SWGROUP_TSECB 30
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#define TEGRA_SWGROUP_NV 31
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#define TEGRA_SWGROUP_NV2 32
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#define TEGRA_SWGROUP_PPCS1 33
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#define TEGRA_SWGROUP_DC1 34
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#define TEGRA_SWGROUP_PPCS2 35
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#define TEGRA_SWGROUP_HC1 36
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#define TEGRA_SWGROUP_SE1 37
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#define TEGRA_SWGROUP_TSEC1 38
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#define TEGRA_SWGROUP_TSECB1 39
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#define TEGRA_SWGROUP_NVDEC1 40
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#define TEGRA210_MC_RESET_AFI 0
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#define TEGRA210_MC_RESET_AVPC 1
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#define TEGRA210_MC_RESET_DC 2
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#define TEGRA210_MC_RESET_DCB 3
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#define TEGRA210_MC_RESET_HC 4
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#define TEGRA210_MC_RESET_HDA 5
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#define TEGRA210_MC_RESET_ISP2 6
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#define TEGRA210_MC_RESET_MPCORE 7
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#define TEGRA210_MC_RESET_NVENC 8
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#define TEGRA210_MC_RESET_PPCS 9
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#define TEGRA210_MC_RESET_SATA 10
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#define TEGRA210_MC_RESET_VI 11
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#define TEGRA210_MC_RESET_VIC 12
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#define TEGRA210_MC_RESET_XUSB_HOST 13
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#define TEGRA210_MC_RESET_XUSB_DEV 14
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#define TEGRA210_MC_RESET_A9AVP 15
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#define TEGRA210_MC_RESET_TSEC 16
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#define TEGRA210_MC_RESET_SDMMC1 17
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#define TEGRA210_MC_RESET_SDMMC2 18
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#define TEGRA210_MC_RESET_SDMMC3 19
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#define TEGRA210_MC_RESET_SDMMC4 20
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#define TEGRA210_MC_RESET_ISP2B 21
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#define TEGRA210_MC_RESET_GPU 22
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#define TEGRA210_MC_RESET_NVDEC 23
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#define TEGRA210_MC_RESET_APE 24
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#define TEGRA210_MC_RESET_SE 25
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#define TEGRA210_MC_RESET_NVJPG 26
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#define TEGRA210_MC_RESET_AXIAP 27
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#define TEGRA210_MC_RESET_ETR 28
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#define TEGRA210_MC_RESET_TSECB 29
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#endif
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