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![Dmitry Baryshkov](/assets/img/avatar_default.png)
Add compatible and constants for the power domains exposed by the RPMH in the Qualcomm SM8450 platform. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20211201072745.3969077-6-vkoul@kernel.org
269 lines
6.4 KiB
C
269 lines
6.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (c) 2018, The Linux Foundation. All rights reserved. */
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#ifndef _DT_BINDINGS_POWER_QCOM_RPMPD_H
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#define _DT_BINDINGS_POWER_QCOM_RPMPD_H
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/* SDM845 Power Domain Indexes */
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#define SDM845_EBI 0
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#define SDM845_MX 1
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#define SDM845_MX_AO 2
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#define SDM845_CX 3
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#define SDM845_CX_AO 4
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#define SDM845_LMX 5
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#define SDM845_LCX 6
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#define SDM845_GFX 7
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#define SDM845_MSS 8
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/* SDX55 Power Domain Indexes */
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#define SDX55_MSS 0
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#define SDX55_MX 1
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#define SDX55_CX 2
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/* SM6350 Power Domain Indexes */
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#define SM6350_CX 0
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#define SM6350_GFX 1
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#define SM6350_LCX 2
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#define SM6350_LMX 3
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#define SM6350_MSS 4
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#define SM6350_MX 5
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/* SM8150 Power Domain Indexes */
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#define SM8150_MSS 0
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#define SM8150_EBI 1
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#define SM8150_LMX 2
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#define SM8150_LCX 3
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#define SM8150_GFX 4
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#define SM8150_MX 5
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#define SM8150_MX_AO 6
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#define SM8150_CX 7
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#define SM8150_CX_AO 8
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#define SM8150_MMCX 9
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#define SM8150_MMCX_AO 10
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/* SM8250 Power Domain Indexes */
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#define SM8250_CX 0
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#define SM8250_CX_AO 1
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#define SM8250_EBI 2
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#define SM8250_GFX 3
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#define SM8250_LCX 4
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#define SM8250_LMX 5
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#define SM8250_MMCX 6
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#define SM8250_MMCX_AO 7
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#define SM8250_MX 8
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#define SM8250_MX_AO 9
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/* SM8350 Power Domain Indexes */
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#define SM8350_CX 0
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#define SM8350_CX_AO 1
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#define SM8350_EBI 2
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#define SM8350_GFX 3
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#define SM8350_LCX 4
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#define SM8350_LMX 5
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#define SM8350_MMCX 6
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#define SM8350_MMCX_AO 7
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#define SM8350_MX 8
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#define SM8350_MX_AO 9
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#define SM8350_MXC 10
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#define SM8350_MXC_AO 11
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#define SM8350_MSS 12
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/* SM8450 Power Domain Indexes */
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#define SM8450_CX 0
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#define SM8450_CX_AO 1
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#define SM8450_EBI 2
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#define SM8450_GFX 3
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#define SM8450_LCX 4
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#define SM8450_LMX 5
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#define SM8450_MMCX 6
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#define SM8450_MMCX_AO 7
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#define SM8450_MX 8
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#define SM8450_MX_AO 9
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#define SM8450_MXC 10
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#define SM8450_MXC_AO 11
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#define SM8450_MSS 12
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/* SC7180 Power Domain Indexes */
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#define SC7180_CX 0
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#define SC7180_CX_AO 1
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#define SC7180_GFX 2
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#define SC7180_MX 3
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#define SC7180_MX_AO 4
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#define SC7180_LMX 5
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#define SC7180_LCX 6
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#define SC7180_MSS 7
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/* SC7280 Power Domain Indexes */
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#define SC7280_CX 0
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#define SC7280_CX_AO 1
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#define SC7280_EBI 2
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#define SC7280_GFX 3
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#define SC7280_MX 4
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#define SC7280_MX_AO 5
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#define SC7280_LMX 6
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#define SC7280_LCX 7
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#define SC7280_MSS 8
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/* SC8180X Power Domain Indexes */
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#define SC8180X_CX 0
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#define SC8180X_CX_AO 1
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#define SC8180X_EBI 2
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#define SC8180X_GFX 3
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#define SC8180X_LCX 4
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#define SC8180X_LMX 5
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#define SC8180X_MMCX 6
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#define SC8180X_MMCX_AO 7
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#define SC8180X_MSS 8
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#define SC8180X_MX 9
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#define SC8180X_MX_AO 10
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/* SDM845 Power Domain performance levels */
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#define RPMH_REGULATOR_LEVEL_RETENTION 16
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#define RPMH_REGULATOR_LEVEL_MIN_SVS 48
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#define RPMH_REGULATOR_LEVEL_LOW_SVS 64
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#define RPMH_REGULATOR_LEVEL_SVS 128
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#define RPMH_REGULATOR_LEVEL_SVS_L0 144
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#define RPMH_REGULATOR_LEVEL_SVS_L1 192
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#define RPMH_REGULATOR_LEVEL_SVS_L2 224
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#define RPMH_REGULATOR_LEVEL_NOM 256
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#define RPMH_REGULATOR_LEVEL_NOM_L1 320
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#define RPMH_REGULATOR_LEVEL_NOM_L2 336
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#define RPMH_REGULATOR_LEVEL_TURBO 384
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#define RPMH_REGULATOR_LEVEL_TURBO_L1 416
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/* MDM9607 Power Domains */
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#define MDM9607_VDDCX 0
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#define MDM9607_VDDCX_AO 1
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#define MDM9607_VDDCX_VFL 2
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#define MDM9607_VDDMX 3
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#define MDM9607_VDDMX_AO 4
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#define MDM9607_VDDMX_VFL 5
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/* MSM8939 Power Domains */
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#define MSM8939_VDDMDCX 0
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#define MSM8939_VDDMDCX_AO 1
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#define MSM8939_VDDMDCX_VFC 2
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#define MSM8939_VDDCX 3
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#define MSM8939_VDDCX_AO 4
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#define MSM8939_VDDCX_VFC 5
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#define MSM8939_VDDMX 6
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#define MSM8939_VDDMX_AO 7
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/* MSM8916 Power Domain Indexes */
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#define MSM8916_VDDCX 0
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#define MSM8916_VDDCX_AO 1
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#define MSM8916_VDDCX_VFC 2
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#define MSM8916_VDDMX 3
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#define MSM8916_VDDMX_AO 4
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/* MSM8953 Power Domain Indexes */
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#define MSM8953_VDDMD 0
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#define MSM8953_VDDMD_AO 1
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#define MSM8953_VDDCX 2
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#define MSM8953_VDDCX_AO 3
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#define MSM8953_VDDCX_VFL 4
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#define MSM8953_VDDMX 5
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#define MSM8953_VDDMX_AO 6
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/* MSM8976 Power Domain Indexes */
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#define MSM8976_VDDCX 0
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#define MSM8976_VDDCX_AO 1
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#define MSM8976_VDDCX_VFL 2
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#define MSM8976_VDDMX 3
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#define MSM8976_VDDMX_AO 4
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#define MSM8976_VDDMX_VFL 5
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/* MSM8994 Power Domain Indexes */
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#define MSM8994_VDDCX 0
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#define MSM8994_VDDCX_AO 1
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#define MSM8994_VDDCX_VFC 2
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#define MSM8994_VDDMX 3
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#define MSM8994_VDDMX_AO 4
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#define MSM8994_VDDGFX 5
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#define MSM8994_VDDGFX_VFC 6
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/* MSM8996 Power Domain Indexes */
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#define MSM8996_VDDCX 0
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#define MSM8996_VDDCX_AO 1
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#define MSM8996_VDDCX_VFC 2
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#define MSM8996_VDDMX 3
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#define MSM8996_VDDMX_AO 4
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#define MSM8996_VDDSSCX 5
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#define MSM8996_VDDSSCX_VFC 6
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/* MSM8998 Power Domain Indexes */
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#define MSM8998_VDDCX 0
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#define MSM8998_VDDCX_AO 1
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#define MSM8998_VDDCX_VFL 2
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#define MSM8998_VDDMX 3
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#define MSM8998_VDDMX_AO 4
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#define MSM8998_VDDMX_VFL 5
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#define MSM8998_SSCCX 6
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#define MSM8998_SSCCX_VFL 7
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#define MSM8998_SSCMX 8
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#define MSM8998_SSCMX_VFL 9
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/* QCS404 Power Domains */
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#define QCS404_VDDMX 0
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#define QCS404_VDDMX_AO 1
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#define QCS404_VDDMX_VFL 2
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#define QCS404_LPICX 3
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#define QCS404_LPICX_VFL 4
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#define QCS404_LPIMX 5
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#define QCS404_LPIMX_VFL 6
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/* SDM660 Power Domains */
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#define SDM660_VDDCX 0
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#define SDM660_VDDCX_AO 1
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#define SDM660_VDDCX_VFL 2
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#define SDM660_VDDMX 3
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#define SDM660_VDDMX_AO 4
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#define SDM660_VDDMX_VFL 5
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#define SDM660_SSCCX 6
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#define SDM660_SSCCX_VFL 7
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#define SDM660_SSCMX 8
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#define SDM660_SSCMX_VFL 9
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/* SM6115 Power Domains */
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#define SM6115_VDDCX 0
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#define SM6115_VDDCX_AO 1
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#define SM6115_VDDCX_VFL 2
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#define SM6115_VDDMX 3
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#define SM6115_VDDMX_AO 4
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#define SM6115_VDDMX_VFL 5
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#define SM6115_VDD_LPI_CX 6
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#define SM6115_VDD_LPI_MX 7
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/* SM6125 Power Domains */
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#define SM6125_VDDCX 0
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#define SM6125_VDDCX_AO 1
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#define SM6125_VDDCX_VFL 2
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#define SM6125_VDDMX 3
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#define SM6125_VDDMX_AO 4
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#define SM6125_VDDMX_VFL 5
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/* QCM2290 Power Domains */
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#define QCM2290_VDDCX 0
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#define QCM2290_VDDCX_AO 1
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#define QCM2290_VDDCX_VFL 2
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#define QCM2290_VDDMX 3
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#define QCM2290_VDDMX_AO 4
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#define QCM2290_VDDMX_VFL 5
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#define QCM2290_VDD_LPI_CX 6
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#define QCM2290_VDD_LPI_MX 7
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/* RPM SMD Power Domain performance levels */
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#define RPM_SMD_LEVEL_RETENTION 16
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#define RPM_SMD_LEVEL_RETENTION_PLUS 32
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#define RPM_SMD_LEVEL_MIN_SVS 48
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#define RPM_SMD_LEVEL_LOW_SVS 64
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#define RPM_SMD_LEVEL_SVS 128
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#define RPM_SMD_LEVEL_SVS_PLUS 192
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#define RPM_SMD_LEVEL_NOM 256
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#define RPM_SMD_LEVEL_NOM_PLUS 320
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#define RPM_SMD_LEVEL_TURBO 384
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#define RPM_SMD_LEVEL_TURBO_NO_CPR 416
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#define RPM_SMD_LEVEL_TURBO_HIGH 448
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#define RPM_SMD_LEVEL_BINNING 512
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#endif
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