mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-27 19:29:37 +00:00
![Marian-Cristian Rotariu](/assets/img/avatar_default.png)
This patch adds power domain indices for the RZ/G2H (r8a774e1) SoC. Signed-off-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/1594138692-16816-5-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
36 lines
1 KiB
C
36 lines
1 KiB
C
/* SPDX-License-Identifier: GPL-2.0
|
|
*
|
|
* Copyright (C) 2020 Renesas Electronics Corp.
|
|
*/
|
|
#ifndef __DT_BINDINGS_POWER_R8A774E1_SYSC_H__
|
|
#define __DT_BINDINGS_POWER_R8A774E1_SYSC_H__
|
|
|
|
/*
|
|
* These power domain indices match the numbers of the interrupt bits
|
|
* representing the power areas in the various Interrupt Registers
|
|
* (e.g. SYSCISR, Interrupt Status Register)
|
|
*/
|
|
|
|
#define R8A774E1_PD_CA57_CPU0 0
|
|
#define R8A774E1_PD_CA57_CPU1 1
|
|
#define R8A774E1_PD_CA57_CPU2 2
|
|
#define R8A774E1_PD_CA57_CPU3 3
|
|
#define R8A774E1_PD_CA53_CPU0 5
|
|
#define R8A774E1_PD_CA53_CPU1 6
|
|
#define R8A774E1_PD_CA53_CPU2 7
|
|
#define R8A774E1_PD_CA53_CPU3 8
|
|
#define R8A774E1_PD_A3VP 9
|
|
#define R8A774E1_PD_CA57_SCU 12
|
|
#define R8A774E1_PD_A3VC 14
|
|
#define R8A774E1_PD_3DG_A 17
|
|
#define R8A774E1_PD_3DG_B 18
|
|
#define R8A774E1_PD_3DG_C 19
|
|
#define R8A774E1_PD_3DG_D 20
|
|
#define R8A774E1_PD_CA53_SCU 21
|
|
#define R8A774E1_PD_3DG_E 22
|
|
#define R8A774E1_PD_A2VC1 26
|
|
|
|
/* Always-on power area */
|
|
#define R8A774E1_PD_ALWAYS_ON 32
|
|
|
|
#endif /* __DT_BINDINGS_POWER_R8A774E1_SYSC_H__ */
|