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Add power domain indices for the R-Car M3-W+ (R8A77961) SoC. Based on Rev. 2.00 of the R-Car Series, 3rd Generation, Hardware User’s Manual (Jul. 31, 2019). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Eugeniu Rosca <erosca@de.adit-jv.com> Link: https://lore.kernel.org/r/20191023122911.12166-6-geert+renesas@glider.be
32 lines
929 B
C
32 lines
929 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2019 Glider bvba
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*/
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#ifndef __DT_BINDINGS_POWER_R8A77961_SYSC_H__
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#define __DT_BINDINGS_POWER_R8A77961_SYSC_H__
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/*
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* These power domain indices match the numbers of the interrupt bits
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* representing the power areas in the various Interrupt Registers
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* (e.g. SYSCISR, Interrupt Status Register)
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*/
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#define R8A77961_PD_CA57_CPU0 0
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#define R8A77961_PD_CA57_CPU1 1
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#define R8A77961_PD_CA53_CPU0 5
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#define R8A77961_PD_CA53_CPU1 6
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#define R8A77961_PD_CA53_CPU2 7
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#define R8A77961_PD_CA53_CPU3 8
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#define R8A77961_PD_CA57_SCU 12
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#define R8A77961_PD_CR7 13
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#define R8A77961_PD_A3VC 14
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#define R8A77961_PD_3DG_A 17
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#define R8A77961_PD_3DG_B 18
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#define R8A77961_PD_CA53_SCU 21
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#define R8A77961_PD_A3IR 24
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#define R8A77961_PD_A2VC1 26
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/* Always-on power area */
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#define R8A77961_PD_ALWAYS_ON 32
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#endif /* __DT_BINDINGS_POWER_R8A77961_SYSC_H__ */
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