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![David S. Miller](/assets/img/avatar_default.png)
Mostly simple cases of overlapping changes (adding code nearby, a function whose name changes, for example). Signed-off-by: David S. Miller <davem@davemloft.net>
685 lines
19 KiB
C
685 lines
19 KiB
C
/*
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* Copyright(c) 2015 EZchip Technologies.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* The full GNU General Public License is included in this distribution in
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* the file called "COPYING".
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*/
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#include <linux/module.h>
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#include <linux/etherdevice.h>
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#include <linux/interrupt.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/of_net.h>
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#include <linux/of_platform.h>
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#include "nps_enet.h"
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#define DRV_NAME "nps_mgt_enet"
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static inline bool nps_enet_is_tx_pending(struct nps_enet_priv *priv)
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{
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u32 tx_ctrl_value = nps_enet_reg_get(priv, NPS_ENET_REG_TX_CTL);
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u32 tx_ctrl_ct = (tx_ctrl_value & TX_CTL_CT_MASK) >> TX_CTL_CT_SHIFT;
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return (!tx_ctrl_ct && priv->tx_skb);
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}
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static void nps_enet_clean_rx_fifo(struct net_device *ndev, u32 frame_len)
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{
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struct nps_enet_priv *priv = netdev_priv(ndev);
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u32 i, len = DIV_ROUND_UP(frame_len, sizeof(u32));
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/* Empty Rx FIFO buffer by reading all words */
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for (i = 0; i < len; i++)
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nps_enet_reg_get(priv, NPS_ENET_REG_RX_BUF);
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}
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static void nps_enet_read_rx_fifo(struct net_device *ndev,
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unsigned char *dst, u32 length)
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{
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struct nps_enet_priv *priv = netdev_priv(ndev);
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s32 i, last = length & (sizeof(u32) - 1);
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u32 *reg = (u32 *)dst, len = length / sizeof(u32);
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bool dst_is_aligned = IS_ALIGNED((unsigned long)dst, sizeof(u32));
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/* In case dst is not aligned we need an intermediate buffer */
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if (dst_is_aligned) {
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ioread32_rep(priv->regs_base + NPS_ENET_REG_RX_BUF, reg, len);
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reg += len;
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} else { /* !dst_is_aligned */
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for (i = 0; i < len; i++, reg++) {
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u32 buf = nps_enet_reg_get(priv, NPS_ENET_REG_RX_BUF);
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put_unaligned_be32(buf, reg);
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}
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}
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/* copy last bytes (if any) */
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if (last) {
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u32 buf;
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ioread32_rep(priv->regs_base + NPS_ENET_REG_RX_BUF, &buf, 1);
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memcpy((u8 *)reg, &buf, last);
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}
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}
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static u32 nps_enet_rx_handler(struct net_device *ndev)
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{
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u32 frame_len, err = 0;
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u32 work_done = 0;
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struct nps_enet_priv *priv = netdev_priv(ndev);
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struct sk_buff *skb;
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u32 rx_ctrl_value = nps_enet_reg_get(priv, NPS_ENET_REG_RX_CTL);
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u32 rx_ctrl_cr = (rx_ctrl_value & RX_CTL_CR_MASK) >> RX_CTL_CR_SHIFT;
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u32 rx_ctrl_er = (rx_ctrl_value & RX_CTL_ER_MASK) >> RX_CTL_ER_SHIFT;
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u32 rx_ctrl_crc = (rx_ctrl_value & RX_CTL_CRC_MASK) >> RX_CTL_CRC_SHIFT;
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frame_len = (rx_ctrl_value & RX_CTL_NR_MASK) >> RX_CTL_NR_SHIFT;
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/* Check if we got RX */
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if (!rx_ctrl_cr)
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return work_done;
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/* If we got here there is a work for us */
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work_done++;
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/* Check Rx error */
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if (rx_ctrl_er) {
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ndev->stats.rx_errors++;
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err = 1;
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}
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/* Check Rx CRC error */
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if (rx_ctrl_crc) {
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ndev->stats.rx_crc_errors++;
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ndev->stats.rx_dropped++;
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err = 1;
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}
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/* Check Frame length Min 64b */
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if (unlikely(frame_len < ETH_ZLEN)) {
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ndev->stats.rx_length_errors++;
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ndev->stats.rx_dropped++;
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err = 1;
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}
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if (err)
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goto rx_irq_clean;
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/* Skb allocation */
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skb = netdev_alloc_skb_ip_align(ndev, frame_len);
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if (unlikely(!skb)) {
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ndev->stats.rx_errors++;
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ndev->stats.rx_dropped++;
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goto rx_irq_clean;
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}
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/* Copy frame from Rx fifo into the skb */
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nps_enet_read_rx_fifo(ndev, skb->data, frame_len);
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skb_put(skb, frame_len);
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skb->protocol = eth_type_trans(skb, ndev);
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skb->ip_summed = CHECKSUM_UNNECESSARY;
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ndev->stats.rx_packets++;
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ndev->stats.rx_bytes += frame_len;
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netif_receive_skb(skb);
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goto rx_irq_frame_done;
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rx_irq_clean:
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/* Clean Rx fifo */
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nps_enet_clean_rx_fifo(ndev, frame_len);
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rx_irq_frame_done:
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/* Ack Rx ctrl register */
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nps_enet_reg_set(priv, NPS_ENET_REG_RX_CTL, 0);
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return work_done;
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}
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static void nps_enet_tx_handler(struct net_device *ndev)
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{
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struct nps_enet_priv *priv = netdev_priv(ndev);
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u32 tx_ctrl_value = nps_enet_reg_get(priv, NPS_ENET_REG_TX_CTL);
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u32 tx_ctrl_et = (tx_ctrl_value & TX_CTL_ET_MASK) >> TX_CTL_ET_SHIFT;
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u32 tx_ctrl_nt = (tx_ctrl_value & TX_CTL_NT_MASK) >> TX_CTL_NT_SHIFT;
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/* Check if we got TX */
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if (!nps_enet_is_tx_pending(priv))
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return;
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/* Ack Tx ctrl register */
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nps_enet_reg_set(priv, NPS_ENET_REG_TX_CTL, 0);
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/* Check Tx transmit error */
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if (unlikely(tx_ctrl_et)) {
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ndev->stats.tx_errors++;
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} else {
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ndev->stats.tx_packets++;
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ndev->stats.tx_bytes += tx_ctrl_nt;
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}
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dev_kfree_skb(priv->tx_skb);
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priv->tx_skb = NULL;
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if (netif_queue_stopped(ndev))
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netif_wake_queue(ndev);
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}
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/**
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* nps_enet_poll - NAPI poll handler.
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* @napi: Pointer to napi_struct structure.
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* @budget: How many frames to process on one call.
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*
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* returns: Number of processed frames
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*/
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static int nps_enet_poll(struct napi_struct *napi, int budget)
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{
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struct net_device *ndev = napi->dev;
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struct nps_enet_priv *priv = netdev_priv(ndev);
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u32 work_done;
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nps_enet_tx_handler(ndev);
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work_done = nps_enet_rx_handler(ndev);
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if ((work_done < budget) && napi_complete_done(napi, work_done)) {
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u32 buf_int_enable_value = 0;
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/* set tx_done and rx_rdy bits */
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buf_int_enable_value |= NPS_ENET_ENABLE << RX_RDY_SHIFT;
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buf_int_enable_value |= NPS_ENET_ENABLE << TX_DONE_SHIFT;
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nps_enet_reg_set(priv, NPS_ENET_REG_BUF_INT_ENABLE,
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buf_int_enable_value);
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/* in case we will get a tx interrupt while interrupts
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* are masked, we will lose it since the tx is edge interrupt.
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* specifically, while executing the code section above,
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* between nps_enet_tx_handler and the interrupts enable, all
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* tx requests will be stuck until we will get an rx interrupt.
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* the two code lines below will solve this situation by
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* re-adding ourselves to the poll list.
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*/
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if (nps_enet_is_tx_pending(priv)) {
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nps_enet_reg_set(priv, NPS_ENET_REG_BUF_INT_ENABLE, 0);
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napi_reschedule(napi);
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}
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}
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return work_done;
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}
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/**
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* nps_enet_irq_handler - Global interrupt handler for ENET.
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* @irq: irq number.
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* @dev_instance: device instance.
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*
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* returns: IRQ_HANDLED for all cases.
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*
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* EZchip ENET has 2 interrupt causes, and depending on bits raised in
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* CTRL registers we may tell what is a reason for interrupt to fire up.
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* We got one for RX and the other for TX (completion).
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*/
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static irqreturn_t nps_enet_irq_handler(s32 irq, void *dev_instance)
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{
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struct net_device *ndev = dev_instance;
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struct nps_enet_priv *priv = netdev_priv(ndev);
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u32 rx_ctrl_value = nps_enet_reg_get(priv, NPS_ENET_REG_RX_CTL);
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u32 rx_ctrl_cr = (rx_ctrl_value & RX_CTL_CR_MASK) >> RX_CTL_CR_SHIFT;
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if (nps_enet_is_tx_pending(priv) || rx_ctrl_cr)
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if (likely(napi_schedule_prep(&priv->napi))) {
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nps_enet_reg_set(priv, NPS_ENET_REG_BUF_INT_ENABLE, 0);
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__napi_schedule(&priv->napi);
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}
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return IRQ_HANDLED;
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}
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static void nps_enet_set_hw_mac_address(struct net_device *ndev)
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{
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struct nps_enet_priv *priv = netdev_priv(ndev);
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u32 ge_mac_cfg_1_value = 0;
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u32 *ge_mac_cfg_2_value = &priv->ge_mac_cfg_2_value;
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/* set MAC address in HW */
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ge_mac_cfg_1_value |= ndev->dev_addr[0] << CFG_1_OCTET_0_SHIFT;
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ge_mac_cfg_1_value |= ndev->dev_addr[1] << CFG_1_OCTET_1_SHIFT;
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ge_mac_cfg_1_value |= ndev->dev_addr[2] << CFG_1_OCTET_2_SHIFT;
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ge_mac_cfg_1_value |= ndev->dev_addr[3] << CFG_1_OCTET_3_SHIFT;
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*ge_mac_cfg_2_value = (*ge_mac_cfg_2_value & ~CFG_2_OCTET_4_MASK)
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| ndev->dev_addr[4] << CFG_2_OCTET_4_SHIFT;
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*ge_mac_cfg_2_value = (*ge_mac_cfg_2_value & ~CFG_2_OCTET_5_MASK)
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| ndev->dev_addr[5] << CFG_2_OCTET_5_SHIFT;
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nps_enet_reg_set(priv, NPS_ENET_REG_GE_MAC_CFG_1,
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ge_mac_cfg_1_value);
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nps_enet_reg_set(priv, NPS_ENET_REG_GE_MAC_CFG_2,
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*ge_mac_cfg_2_value);
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}
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/**
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* nps_enet_hw_reset - Reset the network device.
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* @ndev: Pointer to the network device.
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*
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* This function reset the PCS and TX fifo.
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* The programming model is to set the relevant reset bits
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* wait for some time for this to propagate and then unset
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* the reset bits. This way we ensure that reset procedure
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* is done successfully by device.
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*/
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static void nps_enet_hw_reset(struct net_device *ndev)
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{
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struct nps_enet_priv *priv = netdev_priv(ndev);
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u32 ge_rst_value = 0, phase_fifo_ctl_value = 0;
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/* Pcs reset sequence*/
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ge_rst_value |= NPS_ENET_ENABLE << RST_GMAC_0_SHIFT;
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nps_enet_reg_set(priv, NPS_ENET_REG_GE_RST, ge_rst_value);
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usleep_range(10, 20);
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ge_rst_value = 0;
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nps_enet_reg_set(priv, NPS_ENET_REG_GE_RST, ge_rst_value);
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/* Tx fifo reset sequence */
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phase_fifo_ctl_value |= NPS_ENET_ENABLE << PHASE_FIFO_CTL_RST_SHIFT;
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phase_fifo_ctl_value |= NPS_ENET_ENABLE << PHASE_FIFO_CTL_INIT_SHIFT;
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nps_enet_reg_set(priv, NPS_ENET_REG_PHASE_FIFO_CTL,
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phase_fifo_ctl_value);
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usleep_range(10, 20);
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phase_fifo_ctl_value = 0;
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nps_enet_reg_set(priv, NPS_ENET_REG_PHASE_FIFO_CTL,
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phase_fifo_ctl_value);
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}
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static void nps_enet_hw_enable_control(struct net_device *ndev)
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{
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struct nps_enet_priv *priv = netdev_priv(ndev);
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u32 ge_mac_cfg_0_value = 0, buf_int_enable_value = 0;
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u32 *ge_mac_cfg_2_value = &priv->ge_mac_cfg_2_value;
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u32 *ge_mac_cfg_3_value = &priv->ge_mac_cfg_3_value;
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s32 max_frame_length;
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/* Enable Rx and Tx statistics */
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*ge_mac_cfg_2_value = (*ge_mac_cfg_2_value & ~CFG_2_STAT_EN_MASK)
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| NPS_ENET_GE_MAC_CFG_2_STAT_EN << CFG_2_STAT_EN_SHIFT;
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/* Discard packets with different MAC address */
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*ge_mac_cfg_2_value = (*ge_mac_cfg_2_value & ~CFG_2_DISK_DA_MASK)
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| NPS_ENET_ENABLE << CFG_2_DISK_DA_SHIFT;
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/* Discard multicast packets */
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*ge_mac_cfg_2_value = (*ge_mac_cfg_2_value & ~CFG_2_DISK_MC_MASK)
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| NPS_ENET_ENABLE << CFG_2_DISK_MC_SHIFT;
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nps_enet_reg_set(priv, NPS_ENET_REG_GE_MAC_CFG_2,
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*ge_mac_cfg_2_value);
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/* Discard Packets bigger than max frame length */
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max_frame_length = ETH_HLEN + ndev->mtu + ETH_FCS_LEN;
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if (max_frame_length <= NPS_ENET_MAX_FRAME_LENGTH) {
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*ge_mac_cfg_3_value =
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(*ge_mac_cfg_3_value & ~CFG_3_MAX_LEN_MASK)
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| max_frame_length << CFG_3_MAX_LEN_SHIFT;
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}
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/* Enable interrupts */
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buf_int_enable_value |= NPS_ENET_ENABLE << RX_RDY_SHIFT;
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buf_int_enable_value |= NPS_ENET_ENABLE << TX_DONE_SHIFT;
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nps_enet_reg_set(priv, NPS_ENET_REG_BUF_INT_ENABLE,
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buf_int_enable_value);
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/* Write device MAC address to HW */
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nps_enet_set_hw_mac_address(ndev);
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/* Rx and Tx HW features */
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ge_mac_cfg_0_value |= NPS_ENET_ENABLE << CFG_0_TX_PAD_EN_SHIFT;
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ge_mac_cfg_0_value |= NPS_ENET_ENABLE << CFG_0_TX_CRC_EN_SHIFT;
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ge_mac_cfg_0_value |= NPS_ENET_ENABLE << CFG_0_RX_CRC_STRIP_SHIFT;
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/* IFG configuration */
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ge_mac_cfg_0_value |=
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NPS_ENET_GE_MAC_CFG_0_RX_IFG << CFG_0_RX_IFG_SHIFT;
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ge_mac_cfg_0_value |=
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NPS_ENET_GE_MAC_CFG_0_TX_IFG << CFG_0_TX_IFG_SHIFT;
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/* preamble configuration */
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ge_mac_cfg_0_value |= NPS_ENET_ENABLE << CFG_0_RX_PR_CHECK_EN_SHIFT;
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ge_mac_cfg_0_value |=
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NPS_ENET_GE_MAC_CFG_0_TX_PR_LEN << CFG_0_TX_PR_LEN_SHIFT;
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/* enable flow control frames */
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ge_mac_cfg_0_value |= NPS_ENET_ENABLE << CFG_0_TX_FC_EN_SHIFT;
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ge_mac_cfg_0_value |= NPS_ENET_ENABLE << CFG_0_RX_FC_EN_SHIFT;
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ge_mac_cfg_0_value |=
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NPS_ENET_GE_MAC_CFG_0_TX_FC_RETR << CFG_0_TX_FC_RETR_SHIFT;
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*ge_mac_cfg_3_value = (*ge_mac_cfg_3_value & ~CFG_3_CF_DROP_MASK)
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| NPS_ENET_ENABLE << CFG_3_CF_DROP_SHIFT;
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/* Enable Rx and Tx */
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ge_mac_cfg_0_value |= NPS_ENET_ENABLE << CFG_0_RX_EN_SHIFT;
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ge_mac_cfg_0_value |= NPS_ENET_ENABLE << CFG_0_TX_EN_SHIFT;
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nps_enet_reg_set(priv, NPS_ENET_REG_GE_MAC_CFG_3,
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*ge_mac_cfg_3_value);
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nps_enet_reg_set(priv, NPS_ENET_REG_GE_MAC_CFG_0,
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ge_mac_cfg_0_value);
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}
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static void nps_enet_hw_disable_control(struct net_device *ndev)
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{
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struct nps_enet_priv *priv = netdev_priv(ndev);
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/* Disable interrupts */
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nps_enet_reg_set(priv, NPS_ENET_REG_BUF_INT_ENABLE, 0);
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/* Disable Rx and Tx */
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nps_enet_reg_set(priv, NPS_ENET_REG_GE_MAC_CFG_0, 0);
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}
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static void nps_enet_send_frame(struct net_device *ndev,
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struct sk_buff *skb)
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{
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struct nps_enet_priv *priv = netdev_priv(ndev);
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u32 tx_ctrl_value = 0;
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short length = skb->len;
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u32 i, len = DIV_ROUND_UP(length, sizeof(u32));
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u32 *src = (void *)skb->data;
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bool src_is_aligned = IS_ALIGNED((unsigned long)src, sizeof(u32));
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/* In case src is not aligned we need an intermediate buffer */
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if (src_is_aligned)
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iowrite32_rep(priv->regs_base + NPS_ENET_REG_TX_BUF, src, len);
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else /* !src_is_aligned */
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for (i = 0; i < len; i++, src++)
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nps_enet_reg_set(priv, NPS_ENET_REG_TX_BUF,
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get_unaligned_be32(src));
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/* Write the length of the Frame */
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tx_ctrl_value |= length << TX_CTL_NT_SHIFT;
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tx_ctrl_value |= NPS_ENET_ENABLE << TX_CTL_CT_SHIFT;
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/* Send Frame */
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nps_enet_reg_set(priv, NPS_ENET_REG_TX_CTL, tx_ctrl_value);
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}
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/**
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* nps_enet_set_mac_address - Set the MAC address for this device.
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* @ndev: Pointer to net_device structure.
|
|
* @p: 6 byte Address to be written as MAC address.
|
|
*
|
|
* This function copies the HW address from the sockaddr structure to the
|
|
* net_device structure and updates the address in HW.
|
|
*
|
|
* returns: -EBUSY if the net device is busy or 0 if the address is set
|
|
* successfully.
|
|
*/
|
|
static s32 nps_enet_set_mac_address(struct net_device *ndev, void *p)
|
|
{
|
|
struct sockaddr *addr = p;
|
|
s32 res;
|
|
|
|
if (netif_running(ndev))
|
|
return -EBUSY;
|
|
|
|
res = eth_mac_addr(ndev, p);
|
|
if (!res) {
|
|
ether_addr_copy(ndev->dev_addr, addr->sa_data);
|
|
nps_enet_set_hw_mac_address(ndev);
|
|
}
|
|
|
|
return res;
|
|
}
|
|
|
|
/**
|
|
* nps_enet_set_rx_mode - Change the receive filtering mode.
|
|
* @ndev: Pointer to the network device.
|
|
*
|
|
* This function enables/disables promiscuous mode
|
|
*/
|
|
static void nps_enet_set_rx_mode(struct net_device *ndev)
|
|
{
|
|
struct nps_enet_priv *priv = netdev_priv(ndev);
|
|
u32 ge_mac_cfg_2_value = priv->ge_mac_cfg_2_value;
|
|
|
|
if (ndev->flags & IFF_PROMISC) {
|
|
ge_mac_cfg_2_value = (ge_mac_cfg_2_value & ~CFG_2_DISK_DA_MASK)
|
|
| NPS_ENET_DISABLE << CFG_2_DISK_DA_SHIFT;
|
|
ge_mac_cfg_2_value = (ge_mac_cfg_2_value & ~CFG_2_DISK_MC_MASK)
|
|
| NPS_ENET_DISABLE << CFG_2_DISK_MC_SHIFT;
|
|
|
|
} else {
|
|
ge_mac_cfg_2_value = (ge_mac_cfg_2_value & ~CFG_2_DISK_DA_MASK)
|
|
| NPS_ENET_ENABLE << CFG_2_DISK_DA_SHIFT;
|
|
ge_mac_cfg_2_value = (ge_mac_cfg_2_value & ~CFG_2_DISK_MC_MASK)
|
|
| NPS_ENET_ENABLE << CFG_2_DISK_MC_SHIFT;
|
|
}
|
|
|
|
nps_enet_reg_set(priv, NPS_ENET_REG_GE_MAC_CFG_2, ge_mac_cfg_2_value);
|
|
}
|
|
|
|
/**
|
|
* nps_enet_open - Open the network device.
|
|
* @ndev: Pointer to the network device.
|
|
*
|
|
* returns: 0, on success or non-zero error value on failure.
|
|
*
|
|
* This function sets the MAC address, requests and enables an IRQ
|
|
* for the ENET device and starts the Tx queue.
|
|
*/
|
|
static s32 nps_enet_open(struct net_device *ndev)
|
|
{
|
|
struct nps_enet_priv *priv = netdev_priv(ndev);
|
|
s32 err;
|
|
|
|
/* Reset private variables */
|
|
priv->tx_skb = NULL;
|
|
priv->ge_mac_cfg_2_value = 0;
|
|
priv->ge_mac_cfg_3_value = 0;
|
|
|
|
/* ge_mac_cfg_3 default values */
|
|
priv->ge_mac_cfg_3_value |=
|
|
NPS_ENET_GE_MAC_CFG_3_RX_IFG_TH << CFG_3_RX_IFG_TH_SHIFT;
|
|
|
|
priv->ge_mac_cfg_3_value |=
|
|
NPS_ENET_GE_MAC_CFG_3_MAX_LEN << CFG_3_MAX_LEN_SHIFT;
|
|
|
|
/* Disable HW device */
|
|
nps_enet_hw_disable_control(ndev);
|
|
|
|
/* irq Rx allocation */
|
|
err = request_irq(priv->irq, nps_enet_irq_handler,
|
|
0, "enet-rx-tx", ndev);
|
|
if (err)
|
|
return err;
|
|
|
|
napi_enable(&priv->napi);
|
|
|
|
/* Enable HW device */
|
|
nps_enet_hw_reset(ndev);
|
|
nps_enet_hw_enable_control(ndev);
|
|
|
|
netif_start_queue(ndev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* nps_enet_stop - Close the network device.
|
|
* @ndev: Pointer to the network device.
|
|
*
|
|
* This function stops the Tx queue, disables interrupts for the ENET device.
|
|
*/
|
|
static s32 nps_enet_stop(struct net_device *ndev)
|
|
{
|
|
struct nps_enet_priv *priv = netdev_priv(ndev);
|
|
|
|
napi_disable(&priv->napi);
|
|
netif_stop_queue(ndev);
|
|
nps_enet_hw_disable_control(ndev);
|
|
free_irq(priv->irq, ndev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* nps_enet_start_xmit - Starts the data transmission.
|
|
* @skb: sk_buff pointer that contains data to be Transmitted.
|
|
* @ndev: Pointer to net_device structure.
|
|
*
|
|
* returns: NETDEV_TX_OK, on success
|
|
* NETDEV_TX_BUSY, if any of the descriptors are not free.
|
|
*
|
|
* This function is invoked from upper layers to initiate transmission.
|
|
*/
|
|
static netdev_tx_t nps_enet_start_xmit(struct sk_buff *skb,
|
|
struct net_device *ndev)
|
|
{
|
|
struct nps_enet_priv *priv = netdev_priv(ndev);
|
|
|
|
/* This driver handles one frame at a time */
|
|
netif_stop_queue(ndev);
|
|
|
|
priv->tx_skb = skb;
|
|
|
|
/* make sure tx_skb is actually written to the memory
|
|
* before the HW is informed and the IRQ is fired.
|
|
*/
|
|
wmb();
|
|
|
|
nps_enet_send_frame(ndev, skb);
|
|
|
|
return NETDEV_TX_OK;
|
|
}
|
|
|
|
#ifdef CONFIG_NET_POLL_CONTROLLER
|
|
static void nps_enet_poll_controller(struct net_device *ndev)
|
|
{
|
|
disable_irq(ndev->irq);
|
|
nps_enet_irq_handler(ndev->irq, ndev);
|
|
enable_irq(ndev->irq);
|
|
}
|
|
#endif
|
|
|
|
static const struct net_device_ops nps_netdev_ops = {
|
|
.ndo_open = nps_enet_open,
|
|
.ndo_stop = nps_enet_stop,
|
|
.ndo_start_xmit = nps_enet_start_xmit,
|
|
.ndo_set_mac_address = nps_enet_set_mac_address,
|
|
.ndo_set_rx_mode = nps_enet_set_rx_mode,
|
|
#ifdef CONFIG_NET_POLL_CONTROLLER
|
|
.ndo_poll_controller = nps_enet_poll_controller,
|
|
#endif
|
|
};
|
|
|
|
static s32 nps_enet_probe(struct platform_device *pdev)
|
|
{
|
|
struct device *dev = &pdev->dev;
|
|
struct net_device *ndev;
|
|
struct nps_enet_priv *priv;
|
|
s32 err = 0;
|
|
const char *mac_addr;
|
|
struct resource *res_regs;
|
|
|
|
if (!dev->of_node)
|
|
return -ENODEV;
|
|
|
|
ndev = alloc_etherdev(sizeof(struct nps_enet_priv));
|
|
if (!ndev)
|
|
return -ENOMEM;
|
|
|
|
platform_set_drvdata(pdev, ndev);
|
|
SET_NETDEV_DEV(ndev, dev);
|
|
priv = netdev_priv(ndev);
|
|
|
|
/* The EZ NET specific entries in the device structure. */
|
|
ndev->netdev_ops = &nps_netdev_ops;
|
|
ndev->watchdog_timeo = (400 * HZ / 1000);
|
|
/* FIXME :: no multicast support yet */
|
|
ndev->flags &= ~IFF_MULTICAST;
|
|
|
|
res_regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
priv->regs_base = devm_ioremap_resource(dev, res_regs);
|
|
if (IS_ERR(priv->regs_base)) {
|
|
err = PTR_ERR(priv->regs_base);
|
|
goto out_netdev;
|
|
}
|
|
dev_dbg(dev, "Registers base address is 0x%p\n", priv->regs_base);
|
|
|
|
/* set kernel MAC address to dev */
|
|
mac_addr = of_get_mac_address(dev->of_node);
|
|
if (mac_addr)
|
|
ether_addr_copy(ndev->dev_addr, mac_addr);
|
|
else
|
|
eth_hw_addr_random(ndev);
|
|
|
|
/* Get IRQ number */
|
|
priv->irq = platform_get_irq(pdev, 0);
|
|
if (!priv->irq) {
|
|
dev_err(dev, "failed to retrieve <irq Rx-Tx> value from device tree\n");
|
|
err = -ENODEV;
|
|
goto out_netdev;
|
|
}
|
|
|
|
netif_napi_add(ndev, &priv->napi, nps_enet_poll,
|
|
NPS_ENET_NAPI_POLL_WEIGHT);
|
|
|
|
/* Register the driver. Should be the last thing in probe */
|
|
err = register_netdev(ndev);
|
|
if (err) {
|
|
dev_err(dev, "Failed to register ndev for %s, err = 0x%08x\n",
|
|
ndev->name, (s32)err);
|
|
goto out_netif_api;
|
|
}
|
|
|
|
dev_info(dev, "(rx/tx=%d)\n", priv->irq);
|
|
return 0;
|
|
|
|
out_netif_api:
|
|
netif_napi_del(&priv->napi);
|
|
out_netdev:
|
|
if (err)
|
|
free_netdev(ndev);
|
|
|
|
return err;
|
|
}
|
|
|
|
static s32 nps_enet_remove(struct platform_device *pdev)
|
|
{
|
|
struct net_device *ndev = platform_get_drvdata(pdev);
|
|
struct nps_enet_priv *priv = netdev_priv(ndev);
|
|
|
|
unregister_netdev(ndev);
|
|
free_netdev(ndev);
|
|
netif_napi_del(&priv->napi);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct of_device_id nps_enet_dt_ids[] = {
|
|
{ .compatible = "ezchip,nps-mgt-enet" },
|
|
{ /* Sentinel */ }
|
|
};
|
|
MODULE_DEVICE_TABLE(of, nps_enet_dt_ids);
|
|
|
|
static struct platform_driver nps_enet_driver = {
|
|
.probe = nps_enet_probe,
|
|
.remove = nps_enet_remove,
|
|
.driver = {
|
|
.name = DRV_NAME,
|
|
.of_match_table = nps_enet_dt_ids,
|
|
},
|
|
};
|
|
|
|
module_platform_driver(nps_enet_driver);
|
|
|
|
MODULE_AUTHOR("EZchip Semiconductor");
|
|
MODULE_LICENSE("GPL v2");
|