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![Gregory CLEMENT](/assets/img/avatar_default.png)
The spinlock used by the hwbm functions must be initialized by the
network driver. This commit fixes this lack and the following erros when
lockdep is enabled:
INFO: trying to register non-static key.
the code is fine but needs lockdep annotation.
turning off the locking correctness validator.
[<c010ff80>] (unwind_backtrace) from [<c010bd08>] (show_stack+0x10/0x14)
[<c010bd08>] (show_stack) from [<c032913c>] (dump_stack+0xb4/0xe0)
[<c032913c>] (dump_stack) from [<c01670e4>] (__lock_acquire+0x1f58/0x2060)
[<c01670e4>] (__lock_acquire) from [<c0167dec>] (lock_acquire+0xa4/0xd0)
[<c0167dec>] (lock_acquire) from [<c06f6650>] (_raw_spin_lock_irqsave+0x54/0x68)
[<c06f6650>] (_raw_spin_lock_irqsave) from [<c058e830>] (hwbm_pool_add+0x1c/0xdc)
[<c058e830>] (hwbm_pool_add) from [<c043f4e8>] (mvneta_bm_pool_use+0x338/0x490)
[<c043f4e8>] (mvneta_bm_pool_use) from [<c0443198>] (mvneta_probe+0x654/0x1284)
[<c0443198>] (mvneta_probe) from [<c03b894c>] (platform_drv_probe+0x4c/0xb0)
[<c03b894c>] (platform_drv_probe) from [<c03b7158>] (driver_probe_device+0x214/0x2c0)
[<c03b7158>] (driver_probe_device) from [<c03b72c4>] (__driver_attach+0xc0/0xc4)
[<c03b72c4>] (__driver_attach) from [<c03b5440>] (bus_for_each_dev+0x68/0x9c)
[<c03b5440>] (bus_for_each_dev) from [<c03b65b8>] (bus_add_driver+0x1a0/0x218)
[<c03b65b8>] (bus_add_driver) from [<c03b79cc>] (driver_register+0x78/0xf8)
[<c03b79cc>] (driver_register) from [<c01018f4>] (do_one_initcall+0x90/0x1dc)
[<c01018f4>] (do_one_initcall) from [<c0900de4>] (kernel_init_freeable+0x15c/0x1fc)
[<c0900de4>] (kernel_init_freeable) from [<c06eed90>] (kernel_init+0x8/0x114)
[<c06eed90>] (kernel_init) from [<c0107910>] (ret_from_fork+0x14/0x24)
Fixes: baa11ebc0c
("net: mvneta: Use the new hwbm framework")
Reported-by: Russell King <rmk+kernel@armlinux.org.uk>
Cc: <stable@vger.kernel.org>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
488 lines
13 KiB
C
488 lines
13 KiB
C
/*
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* Driver for Marvell NETA network controller Buffer Manager.
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*
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* Copyright (C) 2015 Marvell
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*
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* Marcin Wojtas <mw@semihalf.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/clk.h>
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#include <linux/genalloc.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/mbus.h>
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#include <linux/module.h>
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#include <linux/netdevice.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/skbuff.h>
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#include <net/hwbm.h>
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#include "mvneta_bm.h"
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#define MVNETA_BM_DRIVER_NAME "mvneta_bm"
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#define MVNETA_BM_DRIVER_VERSION "1.0"
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static void mvneta_bm_write(struct mvneta_bm *priv, u32 offset, u32 data)
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{
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writel(data, priv->reg_base + offset);
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}
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static u32 mvneta_bm_read(struct mvneta_bm *priv, u32 offset)
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{
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return readl(priv->reg_base + offset);
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}
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static void mvneta_bm_pool_enable(struct mvneta_bm *priv, int pool_id)
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{
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u32 val;
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val = mvneta_bm_read(priv, MVNETA_BM_POOL_BASE_REG(pool_id));
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val |= MVNETA_BM_POOL_ENABLE_MASK;
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mvneta_bm_write(priv, MVNETA_BM_POOL_BASE_REG(pool_id), val);
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/* Clear BM cause register */
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mvneta_bm_write(priv, MVNETA_BM_INTR_CAUSE_REG, 0);
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}
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static void mvneta_bm_pool_disable(struct mvneta_bm *priv, int pool_id)
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{
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u32 val;
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val = mvneta_bm_read(priv, MVNETA_BM_POOL_BASE_REG(pool_id));
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val &= ~MVNETA_BM_POOL_ENABLE_MASK;
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mvneta_bm_write(priv, MVNETA_BM_POOL_BASE_REG(pool_id), val);
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}
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static inline void mvneta_bm_config_set(struct mvneta_bm *priv, u32 mask)
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{
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u32 val;
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val = mvneta_bm_read(priv, MVNETA_BM_CONFIG_REG);
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val |= mask;
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mvneta_bm_write(priv, MVNETA_BM_CONFIG_REG, val);
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}
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static inline void mvneta_bm_config_clear(struct mvneta_bm *priv, u32 mask)
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{
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u32 val;
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val = mvneta_bm_read(priv, MVNETA_BM_CONFIG_REG);
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val &= ~mask;
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mvneta_bm_write(priv, MVNETA_BM_CONFIG_REG, val);
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}
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static void mvneta_bm_pool_target_set(struct mvneta_bm *priv, int pool_id,
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u8 target_id, u8 attr)
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{
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u32 val;
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val = mvneta_bm_read(priv, MVNETA_BM_XBAR_POOL_REG(pool_id));
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val &= ~MVNETA_BM_TARGET_ID_MASK(pool_id);
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val &= ~MVNETA_BM_XBAR_ATTR_MASK(pool_id);
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val |= MVNETA_BM_TARGET_ID_VAL(pool_id, target_id);
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val |= MVNETA_BM_XBAR_ATTR_VAL(pool_id, attr);
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mvneta_bm_write(priv, MVNETA_BM_XBAR_POOL_REG(pool_id), val);
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}
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int mvneta_bm_construct(struct hwbm_pool *hwbm_pool, void *buf)
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{
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struct mvneta_bm_pool *bm_pool =
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(struct mvneta_bm_pool *)hwbm_pool->priv;
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struct mvneta_bm *priv = bm_pool->priv;
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dma_addr_t phys_addr;
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/* In order to update buf_cookie field of RX descriptor properly,
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* BM hardware expects buf virtual address to be placed in the
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* first four bytes of mapped buffer.
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*/
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*(u32 *)buf = (u32)buf;
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phys_addr = dma_map_single(&priv->pdev->dev, buf, bm_pool->buf_size,
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DMA_FROM_DEVICE);
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if (unlikely(dma_mapping_error(&priv->pdev->dev, phys_addr)))
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return -ENOMEM;
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mvneta_bm_pool_put_bp(priv, bm_pool, phys_addr);
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return 0;
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}
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EXPORT_SYMBOL_GPL(mvneta_bm_construct);
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/* Create pool */
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static int mvneta_bm_pool_create(struct mvneta_bm *priv,
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struct mvneta_bm_pool *bm_pool)
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{
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struct platform_device *pdev = priv->pdev;
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u8 target_id, attr;
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int size_bytes, err;
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size_bytes = sizeof(u32) * bm_pool->hwbm_pool.size;
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bm_pool->virt_addr = dma_alloc_coherent(&pdev->dev, size_bytes,
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&bm_pool->phys_addr,
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GFP_KERNEL);
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if (!bm_pool->virt_addr)
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return -ENOMEM;
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if (!IS_ALIGNED((u32)bm_pool->virt_addr, MVNETA_BM_POOL_PTR_ALIGN)) {
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dma_free_coherent(&pdev->dev, size_bytes, bm_pool->virt_addr,
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bm_pool->phys_addr);
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dev_err(&pdev->dev, "BM pool %d is not %d bytes aligned\n",
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bm_pool->id, MVNETA_BM_POOL_PTR_ALIGN);
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return -ENOMEM;
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}
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err = mvebu_mbus_get_dram_win_info(bm_pool->phys_addr, &target_id,
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&attr);
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if (err < 0) {
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dma_free_coherent(&pdev->dev, size_bytes, bm_pool->virt_addr,
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bm_pool->phys_addr);
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return err;
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}
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/* Set pool address */
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mvneta_bm_write(priv, MVNETA_BM_POOL_BASE_REG(bm_pool->id),
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bm_pool->phys_addr);
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mvneta_bm_pool_target_set(priv, bm_pool->id, target_id, attr);
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mvneta_bm_pool_enable(priv, bm_pool->id);
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return 0;
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}
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/* Notify the driver that BM pool is being used as specific type and return the
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* pool pointer on success
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*/
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struct mvneta_bm_pool *mvneta_bm_pool_use(struct mvneta_bm *priv, u8 pool_id,
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enum mvneta_bm_type type, u8 port_id,
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int pkt_size)
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{
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struct mvneta_bm_pool *new_pool = &priv->bm_pools[pool_id];
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int num, err;
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if (new_pool->type == MVNETA_BM_LONG &&
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new_pool->port_map != 1 << port_id) {
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dev_err(&priv->pdev->dev,
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"long pool cannot be shared by the ports\n");
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return NULL;
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}
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if (new_pool->type == MVNETA_BM_SHORT && new_pool->type != type) {
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dev_err(&priv->pdev->dev,
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"mixing pools' types between the ports is forbidden\n");
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return NULL;
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}
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if (new_pool->pkt_size == 0 || type != MVNETA_BM_SHORT)
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new_pool->pkt_size = pkt_size;
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/* Allocate buffers in case BM pool hasn't been used yet */
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if (new_pool->type == MVNETA_BM_FREE) {
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struct hwbm_pool *hwbm_pool = &new_pool->hwbm_pool;
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new_pool->priv = priv;
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new_pool->type = type;
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new_pool->buf_size = MVNETA_RX_BUF_SIZE(new_pool->pkt_size);
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hwbm_pool->frag_size =
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SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(new_pool->pkt_size)) +
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SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
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hwbm_pool->construct = mvneta_bm_construct;
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hwbm_pool->priv = new_pool;
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spin_lock_init(&hwbm_pool->lock);
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/* Create new pool */
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err = mvneta_bm_pool_create(priv, new_pool);
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if (err) {
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dev_err(&priv->pdev->dev, "fail to create pool %d\n",
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new_pool->id);
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return NULL;
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}
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/* Allocate buffers for this pool */
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num = hwbm_pool_add(hwbm_pool, hwbm_pool->size, GFP_ATOMIC);
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if (num != hwbm_pool->size) {
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WARN(1, "pool %d: %d of %d allocated\n",
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new_pool->id, num, hwbm_pool->size);
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return NULL;
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}
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}
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return new_pool;
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}
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EXPORT_SYMBOL_GPL(mvneta_bm_pool_use);
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/* Free all buffers from the pool */
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void mvneta_bm_bufs_free(struct mvneta_bm *priv, struct mvneta_bm_pool *bm_pool,
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u8 port_map)
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{
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int i;
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bm_pool->port_map &= ~port_map;
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if (bm_pool->port_map)
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return;
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mvneta_bm_config_set(priv, MVNETA_BM_EMPTY_LIMIT_MASK);
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for (i = 0; i < bm_pool->hwbm_pool.buf_num; i++) {
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dma_addr_t buf_phys_addr;
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u32 *vaddr;
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/* Get buffer physical address (indirect access) */
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buf_phys_addr = mvneta_bm_pool_get_bp(priv, bm_pool);
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/* Work-around to the problems when destroying the pool,
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* when it occurs that a read access to BPPI returns 0.
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*/
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if (buf_phys_addr == 0)
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continue;
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vaddr = phys_to_virt(buf_phys_addr);
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if (!vaddr)
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break;
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dma_unmap_single(&priv->pdev->dev, buf_phys_addr,
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bm_pool->buf_size, DMA_FROM_DEVICE);
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hwbm_buf_free(&bm_pool->hwbm_pool, vaddr);
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}
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mvneta_bm_config_clear(priv, MVNETA_BM_EMPTY_LIMIT_MASK);
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/* Update BM driver with number of buffers removed from pool */
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bm_pool->hwbm_pool.buf_num -= i;
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}
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EXPORT_SYMBOL_GPL(mvneta_bm_bufs_free);
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/* Cleanup pool */
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void mvneta_bm_pool_destroy(struct mvneta_bm *priv,
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struct mvneta_bm_pool *bm_pool, u8 port_map)
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{
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struct hwbm_pool *hwbm_pool = &bm_pool->hwbm_pool;
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bm_pool->port_map &= ~port_map;
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if (bm_pool->port_map)
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return;
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bm_pool->type = MVNETA_BM_FREE;
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mvneta_bm_bufs_free(priv, bm_pool, port_map);
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if (hwbm_pool->buf_num)
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WARN(1, "cannot free all buffers in pool %d\n", bm_pool->id);
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if (bm_pool->virt_addr) {
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dma_free_coherent(&priv->pdev->dev,
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sizeof(u32) * hwbm_pool->size,
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bm_pool->virt_addr, bm_pool->phys_addr);
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bm_pool->virt_addr = NULL;
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}
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mvneta_bm_pool_disable(priv, bm_pool->id);
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}
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EXPORT_SYMBOL_GPL(mvneta_bm_pool_destroy);
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static void mvneta_bm_pools_init(struct mvneta_bm *priv)
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{
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struct device_node *dn = priv->pdev->dev.of_node;
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struct mvneta_bm_pool *bm_pool;
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char prop[15];
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u32 size;
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int i;
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/* Activate BM unit */
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mvneta_bm_write(priv, MVNETA_BM_COMMAND_REG, MVNETA_BM_START_MASK);
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/* Create all pools with maximum size */
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for (i = 0; i < MVNETA_BM_POOLS_NUM; i++) {
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bm_pool = &priv->bm_pools[i];
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bm_pool->id = i;
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bm_pool->type = MVNETA_BM_FREE;
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/* Reset read pointer */
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mvneta_bm_write(priv, MVNETA_BM_POOL_READ_PTR_REG(i), 0);
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/* Reset write pointer */
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mvneta_bm_write(priv, MVNETA_BM_POOL_WRITE_PTR_REG(i), 0);
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/* Configure pool size according to DT or use default value */
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sprintf(prop, "pool%d,capacity", i);
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if (of_property_read_u32(dn, prop, &size)) {
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size = MVNETA_BM_POOL_CAP_DEF;
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} else if (size > MVNETA_BM_POOL_CAP_MAX) {
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dev_warn(&priv->pdev->dev,
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"Illegal pool %d capacity %d, set to %d\n",
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i, size, MVNETA_BM_POOL_CAP_MAX);
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size = MVNETA_BM_POOL_CAP_MAX;
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} else if (size < MVNETA_BM_POOL_CAP_MIN) {
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dev_warn(&priv->pdev->dev,
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"Illegal pool %d capacity %d, set to %d\n",
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i, size, MVNETA_BM_POOL_CAP_MIN);
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size = MVNETA_BM_POOL_CAP_MIN;
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} else if (!IS_ALIGNED(size, MVNETA_BM_POOL_CAP_ALIGN)) {
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dev_warn(&priv->pdev->dev,
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"Illegal pool %d capacity %d, round to %d\n",
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i, size, ALIGN(size,
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MVNETA_BM_POOL_CAP_ALIGN));
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size = ALIGN(size, MVNETA_BM_POOL_CAP_ALIGN);
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}
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bm_pool->hwbm_pool.size = size;
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mvneta_bm_write(priv, MVNETA_BM_POOL_SIZE_REG(i),
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bm_pool->hwbm_pool.size);
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/* Obtain custom pkt_size from DT */
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sprintf(prop, "pool%d,pkt-size", i);
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if (of_property_read_u32(dn, prop, &bm_pool->pkt_size))
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bm_pool->pkt_size = 0;
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}
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}
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static void mvneta_bm_default_set(struct mvneta_bm *priv)
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{
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u32 val;
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/* Mask BM all interrupts */
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mvneta_bm_write(priv, MVNETA_BM_INTR_MASK_REG, 0);
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/* Clear BM cause register */
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mvneta_bm_write(priv, MVNETA_BM_INTR_CAUSE_REG, 0);
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/* Set BM configuration register */
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val = mvneta_bm_read(priv, MVNETA_BM_CONFIG_REG);
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/* Reduce MaxInBurstSize from 32 BPs to 16 BPs */
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val &= ~MVNETA_BM_MAX_IN_BURST_SIZE_MASK;
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val |= MVNETA_BM_MAX_IN_BURST_SIZE_16BP;
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mvneta_bm_write(priv, MVNETA_BM_CONFIG_REG, val);
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}
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static int mvneta_bm_init(struct mvneta_bm *priv)
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{
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mvneta_bm_default_set(priv);
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/* Allocate and initialize BM pools structures */
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priv->bm_pools = devm_kcalloc(&priv->pdev->dev, MVNETA_BM_POOLS_NUM,
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sizeof(struct mvneta_bm_pool),
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GFP_KERNEL);
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if (!priv->bm_pools)
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return -ENOMEM;
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mvneta_bm_pools_init(priv);
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return 0;
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}
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static int mvneta_bm_get_sram(struct device_node *dn,
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struct mvneta_bm *priv)
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{
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priv->bppi_pool = of_gen_pool_get(dn, "internal-mem", 0);
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if (!priv->bppi_pool)
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return -ENOMEM;
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priv->bppi_virt_addr = gen_pool_dma_alloc(priv->bppi_pool,
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MVNETA_BM_BPPI_SIZE,
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&priv->bppi_phys_addr);
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if (!priv->bppi_virt_addr)
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return -ENOMEM;
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return 0;
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}
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static void mvneta_bm_put_sram(struct mvneta_bm *priv)
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{
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gen_pool_free(priv->bppi_pool, priv->bppi_phys_addr,
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MVNETA_BM_BPPI_SIZE);
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}
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static int mvneta_bm_probe(struct platform_device *pdev)
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{
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struct device_node *dn = pdev->dev.of_node;
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struct mvneta_bm *priv;
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struct resource *res;
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int err;
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priv = devm_kzalloc(&pdev->dev, sizeof(struct mvneta_bm), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
priv->reg_base = devm_ioremap_resource(&pdev->dev, res);
|
|
if (IS_ERR(priv->reg_base))
|
|
return PTR_ERR(priv->reg_base);
|
|
|
|
priv->clk = devm_clk_get(&pdev->dev, NULL);
|
|
if (IS_ERR(priv->clk))
|
|
return PTR_ERR(priv->clk);
|
|
err = clk_prepare_enable(priv->clk);
|
|
if (err < 0)
|
|
return err;
|
|
|
|
err = mvneta_bm_get_sram(dn, priv);
|
|
if (err < 0) {
|
|
dev_err(&pdev->dev, "failed to allocate internal memory\n");
|
|
goto err_clk;
|
|
}
|
|
|
|
priv->pdev = pdev;
|
|
|
|
/* Initialize buffer manager internals */
|
|
err = mvneta_bm_init(priv);
|
|
if (err < 0) {
|
|
dev_err(&pdev->dev, "failed to initialize controller\n");
|
|
goto err_sram;
|
|
}
|
|
|
|
dn->data = priv;
|
|
platform_set_drvdata(pdev, priv);
|
|
|
|
dev_info(&pdev->dev, "Buffer Manager for network controller enabled\n");
|
|
|
|
return 0;
|
|
|
|
err_sram:
|
|
mvneta_bm_put_sram(priv);
|
|
err_clk:
|
|
clk_disable_unprepare(priv->clk);
|
|
return err;
|
|
}
|
|
|
|
static int mvneta_bm_remove(struct platform_device *pdev)
|
|
{
|
|
struct mvneta_bm *priv = platform_get_drvdata(pdev);
|
|
u8 all_ports_map = 0xff;
|
|
int i = 0;
|
|
|
|
for (i = 0; i < MVNETA_BM_POOLS_NUM; i++) {
|
|
struct mvneta_bm_pool *bm_pool = &priv->bm_pools[i];
|
|
|
|
mvneta_bm_pool_destroy(priv, bm_pool, all_ports_map);
|
|
}
|
|
|
|
mvneta_bm_put_sram(priv);
|
|
|
|
/* Dectivate BM unit */
|
|
mvneta_bm_write(priv, MVNETA_BM_COMMAND_REG, MVNETA_BM_STOP_MASK);
|
|
|
|
clk_disable_unprepare(priv->clk);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct of_device_id mvneta_bm_match[] = {
|
|
{ .compatible = "marvell,armada-380-neta-bm" },
|
|
{ }
|
|
};
|
|
MODULE_DEVICE_TABLE(of, mvneta_bm_match);
|
|
|
|
static struct platform_driver mvneta_bm_driver = {
|
|
.probe = mvneta_bm_probe,
|
|
.remove = mvneta_bm_remove,
|
|
.driver = {
|
|
.name = MVNETA_BM_DRIVER_NAME,
|
|
.of_match_table = mvneta_bm_match,
|
|
},
|
|
};
|
|
|
|
module_platform_driver(mvneta_bm_driver);
|
|
|
|
MODULE_DESCRIPTION("Marvell NETA Buffer Manager Driver - www.marvell.com");
|
|
MODULE_AUTHOR("Marcin Wojtas <mw@semihalf.com>");
|
|
MODULE_LICENSE("GPL v2");
|