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The CPDMA uses one pool of descriptors for both RX and TX which by default split between all channels proportionally depending on total number of CPDMA channels and number of TX and RX channels. As result, more descriptors will be consumed by TX path if there are more TX channels and there is no way now to dedicate more descriptors for RX path. So, add the ability to re-split CPDMA pool of descriptors between RX and TX path via ethtool '-G' command wich will allow to configure and fix number of descriptors used by RX and TX path, which, then, will be split between RX/TX channels proportionally depending on RX/TX channels number and weight. ethtool '-G' command will accept only number of RX entries and rest of descriptors will be arranged for TX automatically. Command: ethtool -G <devname> rx <number of descriptors> defaults and limitations: - minimum number of rx descriptors is 10% of total number of descriptors in CPDMA pool - maximum number of rx descriptors is 90% of total number of descriptors in CPDMA pool - by default, descriptors will be split equally between RX/TX path - any values passed in "tx" parameter will be ignored Usage: # ethtool -g eth0 Pre-set maximums: RX: 7372 RX Mini: 0 RX Jumbo: 0 TX: 0 Current hardware settings: RX: 4096 RX Mini: 0 RX Jumbo: 0 TX: 4096 # ethtool -G eth0 rx 7372 # ethtool -g eth0 Ring parameters for eth0: Pre-set maximums: RX: 7372 RX Mini: 0 RX Jumbo: 0 TX: 0 Current hardware settings: RX: 7372 RX Mini: 0 RX Jumbo: 0 TX: 820 Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: David S. Miller <davem@davemloft.net>
122 lines
3.9 KiB
C
122 lines
3.9 KiB
C
/*
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* Texas Instruments CPDMA Driver
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*
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* Copyright (C) 2010 Texas Instruments
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __DAVINCI_CPDMA_H__
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#define __DAVINCI_CPDMA_H__
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#define CPDMA_MAX_CHANNELS BITS_PER_LONG
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#define CPDMA_RX_SOURCE_PORT(__status__) ((__status__ >> 16) & 0x7)
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#define CPDMA_EOI_RX_THRESH 0x0
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#define CPDMA_EOI_RX 0x1
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#define CPDMA_EOI_TX 0x2
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#define CPDMA_EOI_MISC 0x3
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struct cpdma_params {
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struct device *dev;
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void __iomem *dmaregs;
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void __iomem *txhdp, *rxhdp, *txcp, *rxcp;
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void __iomem *rxthresh, *rxfree;
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int num_chan;
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bool has_soft_reset;
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int min_packet_size;
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u32 desc_mem_phys;
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u32 desc_hw_addr;
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int desc_mem_size;
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int desc_align;
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u32 bus_freq_mhz;
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u32 descs_pool_size;
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/*
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* Some instances of embedded cpdma controllers have extra control and
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* status registers. The following flag enables access to these
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* "extended" registers.
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*/
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bool has_ext_regs;
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};
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struct cpdma_chan_stats {
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u32 head_enqueue;
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u32 tail_enqueue;
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u32 pad_enqueue;
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u32 misqueued;
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u32 desc_alloc_fail;
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u32 pad_alloc_fail;
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u32 runt_receive_buff;
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u32 runt_transmit_buff;
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u32 empty_dequeue;
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u32 busy_dequeue;
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u32 good_dequeue;
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u32 requeue;
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u32 teardown_dequeue;
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};
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struct cpdma_ctlr;
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struct cpdma_chan;
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typedef void (*cpdma_handler_fn)(void *token, int len, int status);
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struct cpdma_ctlr *cpdma_ctlr_create(struct cpdma_params *params);
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int cpdma_ctlr_destroy(struct cpdma_ctlr *ctlr);
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int cpdma_ctlr_start(struct cpdma_ctlr *ctlr);
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int cpdma_ctlr_stop(struct cpdma_ctlr *ctlr);
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struct cpdma_chan *cpdma_chan_create(struct cpdma_ctlr *ctlr, int chan_num,
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cpdma_handler_fn handler, int rx_type);
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int cpdma_chan_get_rx_buf_num(struct cpdma_chan *chan);
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int cpdma_chan_destroy(struct cpdma_chan *chan);
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int cpdma_chan_start(struct cpdma_chan *chan);
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int cpdma_chan_stop(struct cpdma_chan *chan);
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int cpdma_chan_get_stats(struct cpdma_chan *chan,
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struct cpdma_chan_stats *stats);
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int cpdma_chan_submit(struct cpdma_chan *chan, void *token, void *data,
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int len, int directed);
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int cpdma_chan_process(struct cpdma_chan *chan, int quota);
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int cpdma_ctlr_int_ctrl(struct cpdma_ctlr *ctlr, bool enable);
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void cpdma_ctlr_eoi(struct cpdma_ctlr *ctlr, u32 value);
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int cpdma_chan_int_ctrl(struct cpdma_chan *chan, bool enable);
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u32 cpdma_ctrl_rxchs_state(struct cpdma_ctlr *ctlr);
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u32 cpdma_ctrl_txchs_state(struct cpdma_ctlr *ctlr);
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bool cpdma_check_free_tx_desc(struct cpdma_chan *chan);
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int cpdma_chan_set_weight(struct cpdma_chan *ch, int weight);
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int cpdma_chan_set_rate(struct cpdma_chan *ch, u32 rate);
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u32 cpdma_chan_get_rate(struct cpdma_chan *ch);
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u32 cpdma_chan_get_min_rate(struct cpdma_ctlr *ctlr);
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enum cpdma_control {
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CPDMA_TX_RLIM, /* read-write */
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CPDMA_CMD_IDLE, /* write-only */
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CPDMA_COPY_ERROR_FRAMES, /* read-write */
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CPDMA_RX_OFF_LEN_UPDATE, /* read-write */
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CPDMA_RX_OWNERSHIP_FLIP, /* read-write */
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CPDMA_TX_PRIO_FIXED, /* read-write */
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CPDMA_STAT_IDLE, /* read-only */
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CPDMA_STAT_TX_ERR_CHAN, /* read-only */
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CPDMA_STAT_TX_ERR_CODE, /* read-only */
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CPDMA_STAT_RX_ERR_CHAN, /* read-only */
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CPDMA_STAT_RX_ERR_CODE, /* read-only */
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CPDMA_RX_BUFFER_OFFSET, /* read-write */
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};
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int cpdma_control_get(struct cpdma_ctlr *ctlr, int control);
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int cpdma_control_set(struct cpdma_ctlr *ctlr, int control, int value);
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int cpdma_get_num_rx_descs(struct cpdma_ctlr *ctlr);
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void cpdma_set_num_rx_descs(struct cpdma_ctlr *ctlr, int num_rx_desc);
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int cpdma_get_num_tx_descs(struct cpdma_ctlr *ctlr);
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int cpdma_chan_split_pool(struct cpdma_ctlr *ctlr);
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#endif
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