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![Ingo Molnar](/assets/img/avatar_default.png)
This patch (written by me and also containing many suggestions of Arjan van de Ven) does a major cleanup of the spinlock code. It does the following things: - consolidates and enhances the spinlock/rwlock debugging code - simplifies the asm/spinlock.h files - encapsulates the raw spinlock type and moves generic spinlock features (such as ->break_lock) into the generic code. - cleans up the spinlock code hierarchy to get rid of the spaghetti. Most notably there's now only a single variant of the debugging code, located in lib/spinlock_debug.c. (previously we had one SMP debugging variant per architecture, plus a separate generic one for UP builds) Also, i've enhanced the rwlock debugging facility, it will now track write-owners. There is new spinlock-owner/CPU-tracking on SMP builds too. All locks have lockup detection now, which will work for both soft and hard spin/rwlock lockups. The arch-level include files now only contain the minimally necessary subset of the spinlock code - all the rest that can be generalized now lives in the generic headers: include/asm-i386/spinlock_types.h | 16 include/asm-x86_64/spinlock_types.h | 16 I have also split up the various spinlock variants into separate files, making it easier to see which does what. The new layout is: SMP | UP ----------------------------|----------------------------------- asm/spinlock_types_smp.h | linux/spinlock_types_up.h linux/spinlock_types.h | linux/spinlock_types.h asm/spinlock_smp.h | linux/spinlock_up.h linux/spinlock_api_smp.h | linux/spinlock_api_up.h linux/spinlock.h | linux/spinlock.h /* * here's the role of the various spinlock/rwlock related include files: * * on SMP builds: * * asm/spinlock_types.h: contains the raw_spinlock_t/raw_rwlock_t and the * initializers * * linux/spinlock_types.h: * defines the generic type and initializers * * asm/spinlock.h: contains the __raw_spin_*()/etc. lowlevel * implementations, mostly inline assembly code * * (also included on UP-debug builds:) * * linux/spinlock_api_smp.h: * contains the prototypes for the _spin_*() APIs. * * linux/spinlock.h: builds the final spin_*() APIs. * * on UP builds: * * linux/spinlock_type_up.h: * contains the generic, simplified UP spinlock type. * (which is an empty structure on non-debug builds) * * linux/spinlock_types.h: * defines the generic type and initializers * * linux/spinlock_up.h: * contains the __raw_spin_*()/etc. version of UP * builds. (which are NOPs on non-debug, non-preempt * builds) * * (included on UP-non-debug builds:) * * linux/spinlock_api_up.h: * builds the _spin_*() APIs. * * linux/spinlock.h: builds the final spin_*() APIs. */ All SMP and UP architectures are converted by this patch. arm, i386, ia64, ppc, ppc64, s390/s390x, x64 was build-tested via crosscompilers. m32r, mips, sh, sparc, have not been tested yet, but should be mostly fine. From: Grant Grundler <grundler@parisc-linux.org> Booted and lightly tested on a500-44 (64-bit, SMP kernel, dual CPU). Builds 32-bit SMP kernel (not booted or tested). I did not try to build non-SMP kernels. That should be trivial to fix up later if necessary. I converted bit ops atomic_hash lock to raw_spinlock_t. Doing so avoids some ugly nesting of linux/*.h and asm/*.h files. Those particular locks are well tested and contained entirely inside arch specific code. I do NOT expect any new issues to arise with them. If someone does ever need to use debug/metrics with them, then they will need to unravel this hairball between spinlocks, atomic ops, and bit ops that exist only because parisc has exactly one atomic instruction: LDCW (load and clear word). From: "Luck, Tony" <tony.luck@intel.com> ia64 fix Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Arjan van de Ven <arjanv@infradead.org> Signed-off-by: Grant Grundler <grundler@parisc-linux.org> Cc: Matthew Wilcox <willy@debian.org> Signed-off-by: Hirokazu Takata <takata@linux-m32r.org> Signed-off-by: Mikael Pettersson <mikpe@csd.uu.se> Signed-off-by: Benoit Boissinot <benoit.boissinot@ens-lyon.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
278 lines
6.2 KiB
C
278 lines
6.2 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1999, 2000 by Ralf Baechle
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* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
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*/
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#ifndef _ASM_SPINLOCK_H
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#define _ASM_SPINLOCK_H
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#include <linux/config.h>
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#include <asm/war.h>
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/*
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* Your basic SMP spinlocks, allowing only a single CPU anywhere
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*/
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#define __raw_spin_is_locked(x) ((x)->lock != 0)
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#define __raw_spin_lock_flags(lock, flags) __raw_spin_lock(lock)
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#define __raw_spin_unlock_wait(x) \
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do { cpu_relax(); } while ((x)->lock)
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/*
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* Simple spin lock operations. There are two variants, one clears IRQ's
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* on the local processor, one does not.
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*
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* We make no fairness assumptions. They have a cost.
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*/
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static inline void __raw_spin_lock(raw_spinlock_t *lock)
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{
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unsigned int tmp;
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if (R10000_LLSC_WAR) {
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__asm__ __volatile__(
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" .set noreorder # __raw_spin_lock \n"
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"1: ll %1, %2 \n"
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" bnez %1, 1b \n"
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" li %1, 1 \n"
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" sc %1, %0 \n"
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" beqzl %1, 1b \n"
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" nop \n"
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" sync \n"
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" .set reorder \n"
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: "=m" (lock->lock), "=&r" (tmp)
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: "m" (lock->lock)
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: "memory");
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} else {
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__asm__ __volatile__(
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" .set noreorder # __raw_spin_lock \n"
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"1: ll %1, %2 \n"
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" bnez %1, 1b \n"
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" li %1, 1 \n"
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" sc %1, %0 \n"
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" beqz %1, 1b \n"
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" sync \n"
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" .set reorder \n"
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: "=m" (lock->lock), "=&r" (tmp)
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: "m" (lock->lock)
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: "memory");
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}
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}
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static inline void __raw_spin_unlock(raw_spinlock_t *lock)
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{
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__asm__ __volatile__(
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" .set noreorder # __raw_spin_unlock \n"
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" sync \n"
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" sw $0, %0 \n"
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" .set\treorder \n"
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: "=m" (lock->lock)
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: "m" (lock->lock)
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: "memory");
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}
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static inline unsigned int __raw_spin_trylock(raw_spinlock_t *lock)
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{
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unsigned int temp, res;
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if (R10000_LLSC_WAR) {
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__asm__ __volatile__(
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" .set noreorder # __raw_spin_trylock \n"
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"1: ll %0, %3 \n"
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" ori %2, %0, 1 \n"
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" sc %2, %1 \n"
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" beqzl %2, 1b \n"
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" nop \n"
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" andi %2, %0, 1 \n"
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" sync \n"
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" .set reorder"
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: "=&r" (temp), "=m" (lock->lock), "=&r" (res)
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: "m" (lock->lock)
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: "memory");
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} else {
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__asm__ __volatile__(
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" .set noreorder # __raw_spin_trylock \n"
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"1: ll %0, %3 \n"
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" ori %2, %0, 1 \n"
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" sc %2, %1 \n"
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" beqz %2, 1b \n"
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" andi %2, %0, 1 \n"
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" sync \n"
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" .set reorder"
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: "=&r" (temp), "=m" (lock->lock), "=&r" (res)
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: "m" (lock->lock)
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: "memory");
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}
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return res == 0;
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}
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/*
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* Read-write spinlocks, allowing multiple readers but only one writer.
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*
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* NOTE! it is quite common to have readers in interrupts but no interrupt
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* writers. For those circumstances we can "mix" irq-safe locks - any writer
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* needs to get a irq-safe write-lock, but readers can get non-irqsafe
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* read-locks.
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*/
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static inline void __raw_read_lock(raw_rwlock_t *rw)
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{
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unsigned int tmp;
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if (R10000_LLSC_WAR) {
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__asm__ __volatile__(
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" .set noreorder # __raw_read_lock \n"
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"1: ll %1, %2 \n"
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" bltz %1, 1b \n"
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" addu %1, 1 \n"
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" sc %1, %0 \n"
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" beqzl %1, 1b \n"
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" nop \n"
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" sync \n"
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" .set reorder \n"
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: "=m" (rw->lock), "=&r" (tmp)
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: "m" (rw->lock)
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: "memory");
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} else {
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__asm__ __volatile__(
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" .set noreorder # __raw_read_lock \n"
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"1: ll %1, %2 \n"
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" bltz %1, 1b \n"
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" addu %1, 1 \n"
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" sc %1, %0 \n"
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" beqz %1, 1b \n"
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" sync \n"
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" .set reorder \n"
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: "=m" (rw->lock), "=&r" (tmp)
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: "m" (rw->lock)
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: "memory");
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}
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}
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/* Note the use of sub, not subu which will make the kernel die with an
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overflow exception if we ever try to unlock an rwlock that is already
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unlocked or is being held by a writer. */
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static inline void __raw_read_unlock(raw_rwlock_t *rw)
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{
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unsigned int tmp;
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if (R10000_LLSC_WAR) {
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__asm__ __volatile__(
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"1: ll %1, %2 # __raw_read_unlock \n"
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" sub %1, 1 \n"
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" sc %1, %0 \n"
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" beqzl %1, 1b \n"
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" sync \n"
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: "=m" (rw->lock), "=&r" (tmp)
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: "m" (rw->lock)
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: "memory");
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} else {
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__asm__ __volatile__(
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" .set noreorder # __raw_read_unlock \n"
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"1: ll %1, %2 \n"
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" sub %1, 1 \n"
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" sc %1, %0 \n"
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" beqz %1, 1b \n"
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" sync \n"
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" .set reorder \n"
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: "=m" (rw->lock), "=&r" (tmp)
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: "m" (rw->lock)
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: "memory");
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}
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}
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static inline void __raw_write_lock(raw_rwlock_t *rw)
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{
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unsigned int tmp;
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if (R10000_LLSC_WAR) {
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__asm__ __volatile__(
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" .set noreorder # __raw_write_lock \n"
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"1: ll %1, %2 \n"
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" bnez %1, 1b \n"
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" lui %1, 0x8000 \n"
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" sc %1, %0 \n"
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" beqzl %1, 1b \n"
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" nop \n"
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" sync \n"
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" .set reorder \n"
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: "=m" (rw->lock), "=&r" (tmp)
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: "m" (rw->lock)
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: "memory");
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} else {
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__asm__ __volatile__(
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" .set noreorder # __raw_write_lock \n"
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"1: ll %1, %2 \n"
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" bnez %1, 1b \n"
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" lui %1, 0x8000 \n"
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" sc %1, %0 \n"
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" beqz %1, 1b \n"
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" nop \n"
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" sync \n"
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" .set reorder \n"
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: "=m" (rw->lock), "=&r" (tmp)
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: "m" (rw->lock)
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: "memory");
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}
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}
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static inline void __raw_write_unlock(raw_rwlock_t *rw)
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{
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__asm__ __volatile__(
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" sync # __raw_write_unlock \n"
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" sw $0, %0 \n"
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: "=m" (rw->lock)
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: "m" (rw->lock)
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: "memory");
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}
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#define __raw_read_trylock(lock) generic__raw_read_trylock(lock)
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static inline int __raw_write_trylock(raw_rwlock_t *rw)
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{
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unsigned int tmp;
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int ret;
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if (R10000_LLSC_WAR) {
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__asm__ __volatile__(
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" .set noreorder # __raw_write_trylock \n"
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" li %2, 0 \n"
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"1: ll %1, %3 \n"
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" bnez %1, 2f \n"
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" lui %1, 0x8000 \n"
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" sc %1, %0 \n"
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" beqzl %1, 1b \n"
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" nop \n"
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" sync \n"
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" li %2, 1 \n"
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" .set reorder \n"
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"2: \n"
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: "=m" (rw->lock), "=&r" (tmp), "=&r" (ret)
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: "m" (rw->lock)
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: "memory");
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} else {
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__asm__ __volatile__(
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" .set noreorder # __raw_write_trylock \n"
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" li %2, 0 \n"
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"1: ll %1, %3 \n"
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" bnez %1, 2f \n"
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" lui %1, 0x8000 \n"
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" sc %1, %0 \n"
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" beqz %1, 1b \n"
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" sync \n"
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" li %2, 1 \n"
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" .set reorder \n"
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"2: \n"
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: "=m" (rw->lock), "=&r" (tmp), "=&r" (ret)
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: "m" (rw->lock)
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: "memory");
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}
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return ret;
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}
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#endif /* _ASM_SPINLOCK_H */
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