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7198e6b031
Add initial support for a3xx 3d core.
So far, with hardware that I've seen to date, we can have:
+ zero, one, or two z180 2d cores
+ a3xx or a2xx 3d core, which share a common CP (the firmware
for the CP seems to implement some different PM4 packet types
but the basics of cmdstream submission are the same)
Which means that the eventual complete "class" hierarchy, once
support for all past and present hw is in place, becomes:
+ msm_gpu
+ adreno_gpu
+ a3xx_gpu
+ a2xx_gpu
+ z180_gpu
This commit splits out the parts that will eventually be common
between a2xx/a3xx into adreno_gpu, and the parts that are even
common to z180 into msm_gpu.
Note that there is no cmdstream validation required. All memory access
from the GPU is via IOMMU/MMU. So as long as you don't map silly things
to the GPU, there isn't much damage that the GPU can do.
Signed-off-by: Rob Clark <robdclark@gmail.com>
207 lines
7.8 KiB
C
207 lines
7.8 KiB
C
/*
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* Copyright (C) 2013 Red Hat
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* Author: Rob Clark <robdclark@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __MSM_DRM_H__
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#define __MSM_DRM_H__
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#include <stddef.h>
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#include <drm/drm.h>
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/* Please note that modifications to all structs defined here are
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* subject to backwards-compatibility constraints:
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* 1) Do not use pointers, use uint64_t instead for 32 bit / 64 bit
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* user/kernel compatibility
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* 2) Keep fields aligned to their size
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* 3) Because of how drm_ioctl() works, we can add new fields at
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* the end of an ioctl if some care is taken: drm_ioctl() will
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* zero out the new fields at the tail of the ioctl, so a zero
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* value should have a backwards compatible meaning. And for
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* output params, userspace won't see the newly added output
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* fields.. so that has to be somehow ok.
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*/
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#define MSM_PIPE_NONE 0x00
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#define MSM_PIPE_2D0 0x01
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#define MSM_PIPE_2D1 0x02
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#define MSM_PIPE_3D0 0x10
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/* timeouts are specified in clock-monotonic absolute times (to simplify
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* restarting interrupted ioctls). The following struct is logically the
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* same as 'struct timespec' but 32/64b ABI safe.
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*/
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struct drm_msm_timespec {
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int64_t tv_sec; /* seconds */
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int64_t tv_nsec; /* nanoseconds */
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};
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#define MSM_PARAM_GPU_ID 0x01
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#define MSM_PARAM_GMEM_SIZE 0x02
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struct drm_msm_param {
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uint32_t pipe; /* in, MSM_PIPE_x */
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uint32_t param; /* in, MSM_PARAM_x */
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uint64_t value; /* out (get_param) or in (set_param) */
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};
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/*
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* GEM buffers:
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*/
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#define MSM_BO_SCANOUT 0x00000001 /* scanout capable */
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#define MSM_BO_GPU_READONLY 0x00000002
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#define MSM_BO_CACHE_MASK 0x000f0000
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/* cache modes */
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#define MSM_BO_CACHED 0x00010000
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#define MSM_BO_WC 0x00020000
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#define MSM_BO_UNCACHED 0x00040000
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struct drm_msm_gem_new {
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uint64_t size; /* in */
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uint32_t flags; /* in, mask of MSM_BO_x */
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uint32_t handle; /* out */
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};
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struct drm_msm_gem_info {
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uint32_t handle; /* in */
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uint32_t pad;
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uint64_t offset; /* out, offset to pass to mmap() */
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};
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#define MSM_PREP_READ 0x01
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#define MSM_PREP_WRITE 0x02
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#define MSM_PREP_NOSYNC 0x04
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struct drm_msm_gem_cpu_prep {
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uint32_t handle; /* in */
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uint32_t op; /* in, mask of MSM_PREP_x */
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struct drm_msm_timespec timeout; /* in */
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};
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struct drm_msm_gem_cpu_fini {
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uint32_t handle; /* in */
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};
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/*
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* Cmdstream Submission:
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*/
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/* The value written into the cmdstream is logically:
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*
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* ((relocbuf->gpuaddr + reloc_offset) << shift) | or
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*
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* When we have GPU's w/ >32bit ptrs, it should be possible to deal
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* with this by emit'ing two reloc entries with appropriate shift
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* values. Or a new MSM_SUBMIT_CMD_x type would also be an option.
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*
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* NOTE that reloc's must be sorted by order of increasing submit_offset,
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* otherwise EINVAL.
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*/
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struct drm_msm_gem_submit_reloc {
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uint32_t submit_offset; /* in, offset from submit_bo */
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uint32_t or; /* in, value OR'd with result */
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int32_t shift; /* in, amount of left shift (can be negative) */
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uint32_t reloc_idx; /* in, index of reloc_bo buffer */
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uint64_t reloc_offset; /* in, offset from start of reloc_bo */
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};
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/* submit-types:
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* BUF - this cmd buffer is executed normally.
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* IB_TARGET_BUF - this cmd buffer is an IB target. Reloc's are
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* processed normally, but the kernel does not setup an IB to
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* this buffer in the first-level ringbuffer
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* CTX_RESTORE_BUF - only executed if there has been a GPU context
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* switch since the last SUBMIT ioctl
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*/
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#define MSM_SUBMIT_CMD_BUF 0x0001
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#define MSM_SUBMIT_CMD_IB_TARGET_BUF 0x0002
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#define MSM_SUBMIT_CMD_CTX_RESTORE_BUF 0x0003
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struct drm_msm_gem_submit_cmd {
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uint32_t type; /* in, one of MSM_SUBMIT_CMD_x */
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uint32_t submit_idx; /* in, index of submit_bo cmdstream buffer */
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uint32_t submit_offset; /* in, offset into submit_bo */
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uint32_t size; /* in, cmdstream size */
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uint32_t pad;
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uint32_t nr_relocs; /* in, number of submit_reloc's */
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uint64_t __user relocs; /* in, ptr to array of submit_reloc's */
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};
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/* Each buffer referenced elsewhere in the cmdstream submit (ie. the
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* cmdstream buffer(s) themselves or reloc entries) has one (and only
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* one) entry in the submit->bos[] table.
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*
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* As a optimization, the current buffer (gpu virtual address) can be
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* passed back through the 'presumed' field. If on a subsequent reloc,
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* userspace passes back a 'presumed' address that is still valid,
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* then patching the cmdstream for this entry is skipped. This can
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* avoid kernel needing to map/access the cmdstream bo in the common
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* case.
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*/
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#define MSM_SUBMIT_BO_READ 0x0001
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#define MSM_SUBMIT_BO_WRITE 0x0002
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struct drm_msm_gem_submit_bo {
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uint32_t flags; /* in, mask of MSM_SUBMIT_BO_x */
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uint32_t handle; /* in, GEM handle */
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uint64_t presumed; /* in/out, presumed buffer address */
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};
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/* Each cmdstream submit consists of a table of buffers involved, and
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* one or more cmdstream buffers. This allows for conditional execution
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* (context-restore), and IB buffers needed for per tile/bin draw cmds.
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*/
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struct drm_msm_gem_submit {
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uint32_t pipe; /* in, MSM_PIPE_x */
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uint32_t fence; /* out */
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uint32_t nr_bos; /* in, number of submit_bo's */
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uint32_t nr_cmds; /* in, number of submit_cmd's */
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uint64_t __user bos; /* in, ptr to array of submit_bo's */
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uint64_t __user cmds; /* in, ptr to array of submit_cmd's */
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};
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/* The normal way to synchronize with the GPU is just to CPU_PREP on
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* a buffer if you need to access it from the CPU (other cmdstream
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* submission from same or other contexts, PAGE_FLIP ioctl, etc, all
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* handle the required synchronization under the hood). This ioctl
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* mainly just exists as a way to implement the gallium pipe_fence
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* APIs without requiring a dummy bo to synchronize on.
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*/
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struct drm_msm_wait_fence {
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uint32_t fence; /* in */
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uint32_t pad;
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struct drm_msm_timespec timeout; /* in */
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};
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#define DRM_MSM_GET_PARAM 0x00
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/* placeholder:
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#define DRM_MSM_SET_PARAM 0x01
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*/
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#define DRM_MSM_GEM_NEW 0x02
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#define DRM_MSM_GEM_INFO 0x03
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#define DRM_MSM_GEM_CPU_PREP 0x04
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#define DRM_MSM_GEM_CPU_FINI 0x05
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#define DRM_MSM_GEM_SUBMIT 0x06
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#define DRM_MSM_WAIT_FENCE 0x07
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#define DRM_MSM_NUM_IOCTLS 0x08
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#define DRM_IOCTL_MSM_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GET_PARAM, struct drm_msm_param)
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#define DRM_IOCTL_MSM_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_NEW, struct drm_msm_gem_new)
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#define DRM_IOCTL_MSM_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_INFO, struct drm_msm_gem_info)
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#define DRM_IOCTL_MSM_GEM_CPU_PREP DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_PREP, struct drm_msm_gem_cpu_prep)
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#define DRM_IOCTL_MSM_GEM_CPU_FINI DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_FINI, struct drm_msm_gem_cpu_fini)
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#define DRM_IOCTL_MSM_GEM_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_SUBMIT, struct drm_msm_gem_submit)
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#define DRM_IOCTL_MSM_WAIT_FENCE DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_WAIT_FENCE, struct drm_msm_wait_fence)
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#endif /* __MSM_DRM_H__ */
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