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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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6606c3e0da
Implement lazy MMU update hooks which are SMP safe for both direct and shadow page tables. The idea is that PTE updates and page invalidations while in lazy mode can be batched into a single hypercall. We use this in VMI for shadow page table synchronization, and it is a win. It also can be used by PPC and for direct page tables on Xen. For SMP, the enter / leave must happen under protection of the page table locks for page tables which are being modified. This is because otherwise, you end up with stale state in the batched hypercall, which other CPUs can race ahead of. Doing this under the protection of the locks guarantees the synchronization is correct, and also means that spurious faults which are generated during this window by remote CPUs are properly handled, as the page fault handler must re-check the PTE under protection of the same lock. Signed-off-by: Zachary Amsden <zach@vmware.com> Signed-off-by: Jeremy Fitzhardinge <jeremy@xensource.com> Cc: Rusty Russell <rusty@rustcorp.com.au> Cc: Andi Kleen <ak@suse.de> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
261 lines
7.3 KiB
C
261 lines
7.3 KiB
C
#ifndef _ASM_GENERIC_PGTABLE_H
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#define _ASM_GENERIC_PGTABLE_H
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#ifndef __ASSEMBLY__
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#ifndef __HAVE_ARCH_PTEP_ESTABLISH
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/*
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* Establish a new mapping:
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* - flush the old one
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* - update the page tables
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* - inform the TLB about the new one
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*
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* We hold the mm semaphore for reading, and the pte lock.
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*
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* Note: the old pte is known to not be writable, so we don't need to
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* worry about dirty bits etc getting lost.
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*/
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#ifndef __HAVE_ARCH_SET_PTE_ATOMIC
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#define ptep_establish(__vma, __address, __ptep, __entry) \
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do { \
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set_pte_at((__vma)->vm_mm, (__address), __ptep, __entry); \
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flush_tlb_page(__vma, __address); \
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} while (0)
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#else /* __HAVE_ARCH_SET_PTE_ATOMIC */
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#define ptep_establish(__vma, __address, __ptep, __entry) \
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do { \
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set_pte_atomic(__ptep, __entry); \
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flush_tlb_page(__vma, __address); \
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} while (0)
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#endif /* __HAVE_ARCH_SET_PTE_ATOMIC */
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#endif
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#ifndef __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
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/*
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* Largely same as above, but only sets the access flags (dirty,
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* accessed, and writable). Furthermore, we know it always gets set
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* to a "more permissive" setting, which allows most architectures
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* to optimize this.
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*/
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#define ptep_set_access_flags(__vma, __address, __ptep, __entry, __dirty) \
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do { \
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set_pte_at((__vma)->vm_mm, (__address), __ptep, __entry); \
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flush_tlb_page(__vma, __address); \
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} while (0)
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#endif
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#ifndef __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
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#define ptep_test_and_clear_young(__vma, __address, __ptep) \
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({ \
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pte_t __pte = *(__ptep); \
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int r = 1; \
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if (!pte_young(__pte)) \
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r = 0; \
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else \
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set_pte_at((__vma)->vm_mm, (__address), \
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(__ptep), pte_mkold(__pte)); \
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r; \
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})
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#endif
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#ifndef __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH
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#define ptep_clear_flush_young(__vma, __address, __ptep) \
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({ \
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int __young; \
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__young = ptep_test_and_clear_young(__vma, __address, __ptep); \
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if (__young) \
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flush_tlb_page(__vma, __address); \
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__young; \
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})
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#endif
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#ifndef __HAVE_ARCH_PTEP_TEST_AND_CLEAR_DIRTY
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#define ptep_test_and_clear_dirty(__vma, __address, __ptep) \
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({ \
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pte_t __pte = *__ptep; \
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int r = 1; \
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if (!pte_dirty(__pte)) \
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r = 0; \
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else \
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set_pte_at((__vma)->vm_mm, (__address), (__ptep), \
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pte_mkclean(__pte)); \
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r; \
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})
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#endif
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#ifndef __HAVE_ARCH_PTEP_CLEAR_DIRTY_FLUSH
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#define ptep_clear_flush_dirty(__vma, __address, __ptep) \
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({ \
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int __dirty; \
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__dirty = ptep_test_and_clear_dirty(__vma, __address, __ptep); \
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if (__dirty) \
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flush_tlb_page(__vma, __address); \
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__dirty; \
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})
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#endif
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#ifndef __HAVE_ARCH_PTEP_GET_AND_CLEAR
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#define ptep_get_and_clear(__mm, __address, __ptep) \
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({ \
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pte_t __pte = *(__ptep); \
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pte_clear((__mm), (__address), (__ptep)); \
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__pte; \
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})
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#endif
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#ifndef __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL
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#define ptep_get_and_clear_full(__mm, __address, __ptep, __full) \
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({ \
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pte_t __pte; \
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__pte = ptep_get_and_clear((__mm), (__address), (__ptep)); \
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__pte; \
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})
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#endif
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/*
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* Some architectures may be able to avoid expensive synchronization
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* primitives when modifications are made to PTE's which are already
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* not present, or in the process of an address space destruction.
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*/
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#ifndef __HAVE_ARCH_PTE_CLEAR_NOT_PRESENT_FULL
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#define pte_clear_not_present_full(__mm, __address, __ptep, __full) \
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do { \
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pte_clear((__mm), (__address), (__ptep)); \
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} while (0)
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#endif
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#ifndef __HAVE_ARCH_PTEP_CLEAR_FLUSH
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#define ptep_clear_flush(__vma, __address, __ptep) \
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({ \
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pte_t __pte; \
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__pte = ptep_get_and_clear((__vma)->vm_mm, __address, __ptep); \
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flush_tlb_page(__vma, __address); \
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__pte; \
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})
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#endif
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#ifndef __HAVE_ARCH_PTEP_SET_WRPROTECT
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struct mm_struct;
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static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long address, pte_t *ptep)
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{
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pte_t old_pte = *ptep;
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set_pte_at(mm, address, ptep, pte_wrprotect(old_pte));
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}
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#endif
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#ifndef __HAVE_ARCH_PTE_SAME
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#define pte_same(A,B) (pte_val(A) == pte_val(B))
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#endif
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#ifndef __HAVE_ARCH_PAGE_TEST_AND_CLEAR_DIRTY
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#define page_test_and_clear_dirty(page) (0)
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#define pte_maybe_dirty(pte) pte_dirty(pte)
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#else
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#define pte_maybe_dirty(pte) (1)
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#endif
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#ifndef __HAVE_ARCH_PAGE_TEST_AND_CLEAR_YOUNG
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#define page_test_and_clear_young(page) (0)
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#endif
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#ifndef __HAVE_ARCH_PGD_OFFSET_GATE
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#define pgd_offset_gate(mm, addr) pgd_offset(mm, addr)
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#endif
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#ifndef __HAVE_ARCH_LAZY_MMU_PROT_UPDATE
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#define lazy_mmu_prot_update(pte) do { } while (0)
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#endif
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#ifndef __HAVE_ARCH_MOVE_PTE
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#define move_pte(pte, prot, old_addr, new_addr) (pte)
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#endif
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/*
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* A facility to provide lazy MMU batching. This allows PTE updates and
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* page invalidations to be delayed until a call to leave lazy MMU mode
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* is issued. Some architectures may benefit from doing this, and it is
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* beneficial for both shadow and direct mode hypervisors, which may batch
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* the PTE updates which happen during this window. Note that using this
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* interface requires that read hazards be removed from the code. A read
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* hazard could result in the direct mode hypervisor case, since the actual
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* write to the page tables may not yet have taken place, so reads though
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* a raw PTE pointer after it has been modified are not guaranteed to be
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* up to date. This mode can only be entered and left under the protection of
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* the page table locks for all page tables which may be modified. In the UP
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* case, this is required so that preemption is disabled, and in the SMP case,
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* it must synchronize the delayed page table writes properly on other CPUs.
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*/
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#ifndef __HAVE_ARCH_ENTER_LAZY_MMU_MODE
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#define arch_enter_lazy_mmu_mode() do {} while (0)
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#define arch_leave_lazy_mmu_mode() do {} while (0)
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#endif
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/*
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* When walking page tables, get the address of the next boundary,
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* or the end address of the range if that comes earlier. Although no
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* vma end wraps to 0, rounded up __boundary may wrap to 0 throughout.
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*/
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#define pgd_addr_end(addr, end) \
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({ unsigned long __boundary = ((addr) + PGDIR_SIZE) & PGDIR_MASK; \
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(__boundary - 1 < (end) - 1)? __boundary: (end); \
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})
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#ifndef pud_addr_end
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#define pud_addr_end(addr, end) \
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({ unsigned long __boundary = ((addr) + PUD_SIZE) & PUD_MASK; \
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(__boundary - 1 < (end) - 1)? __boundary: (end); \
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})
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#endif
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#ifndef pmd_addr_end
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#define pmd_addr_end(addr, end) \
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({ unsigned long __boundary = ((addr) + PMD_SIZE) & PMD_MASK; \
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(__boundary - 1 < (end) - 1)? __boundary: (end); \
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})
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#endif
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/*
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* When walking page tables, we usually want to skip any p?d_none entries;
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* and any p?d_bad entries - reporting the error before resetting to none.
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* Do the tests inline, but report and clear the bad entry in mm/memory.c.
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*/
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void pgd_clear_bad(pgd_t *);
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void pud_clear_bad(pud_t *);
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void pmd_clear_bad(pmd_t *);
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static inline int pgd_none_or_clear_bad(pgd_t *pgd)
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{
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if (pgd_none(*pgd))
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return 1;
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if (unlikely(pgd_bad(*pgd))) {
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pgd_clear_bad(pgd);
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return 1;
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}
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return 0;
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}
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static inline int pud_none_or_clear_bad(pud_t *pud)
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{
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if (pud_none(*pud))
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return 1;
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if (unlikely(pud_bad(*pud))) {
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pud_clear_bad(pud);
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return 1;
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}
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return 0;
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}
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static inline int pmd_none_or_clear_bad(pmd_t *pmd)
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{
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if (pmd_none(*pmd))
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return 1;
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if (unlikely(pmd_bad(*pmd))) {
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pmd_clear_bad(pmd);
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return 1;
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}
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return 0;
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}
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#endif /* !__ASSEMBLY__ */
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#endif /* _ASM_GENERIC_PGTABLE_H */
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