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![Cho KyongHo](/assets/img/avatar_default.png)
This patch contains 2 workaround for the System MMU v3.x. System MMU v3.2 and v3.3 has FLPD cache that caches first level page table entries to reduce page table walking latency. However, the FLPD cache is filled with a first level page table entry even though it is not accessed by a master H/W because System MMU v3.3 speculatively prefetches page table entries that may be accessed in the near future by the master H/W. The prefetched FLPD cache entries are not invalidated by iommu_unmap() because iommu_unmap() only unmaps and invalidates the page table entries that is mapped. Because exynos-iommu driver discards a second level page table when it needs to be replaced with another second level page table or a first level page table entry with 1MB mapping, It is required to invalidate FLPD cache that may contain the first level page table entry that points to the second level page table. Another workaround of System MMU v3.3 is initializing the first level page table entries with the second level page table which is filled with all zeros. This prevents System MMU prefetches 'fault' first level page table entry which may lead page fault on access to 16MiB wide. System MMU 3.x fetches consecutive page table entries by a page table walking to maximize bus utilization and to minimize TLB miss panelty. Unfortunately, functional problem is raised with the fetching behavior because it fetches 'fault' page table entries that specifies no translation information and that a valid translation information will be written to in the near future. The logic in the System MMU generates page fault with the cached fault entries that is no longer coherent with the page table which is updated. There is another workaround that must be implemented by I/O virtual memory manager: any two consecutive I/O virtual memory area must have a hole between the two that is larger than or equal to 128KiB. Also, next I/O virtual memory area must be started from the next 128KiB boundary. 0 128K 256K 384K 512K |-------------|---------------|-----------------|----------------| |area1---------------->|.........hole...........|<--- area2 ----- The constraint is depicted above. The size is selected by the calculation followed: - System MMU can fetch consecutive 64 page table entries at once 64 * 4KiB = 256KiB. This is the size between 128K ~ 384K of the above picture. This style of fetching is 'block fetch'. It fetches the page table entries predefined consecutive page table entries including the entry that is the reason of the page table walking. - System MMU can prefetch upto consecutive 32 page table entries. This is the size between 256K ~ 384K. Signed-off-by: Cho KyongHo <pullip.cho@samsung.com> Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
1224 lines
31 KiB
C
1224 lines
31 KiB
C
/* linux/drivers/iommu/exynos_iommu.c
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*
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* Copyright (c) 2011 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifdef CONFIG_EXYNOS_IOMMU_DEBUG
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#define DEBUG
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#endif
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#include <linux/io.h>
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#include <linux/interrupt.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/pm_runtime.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/mm.h>
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#include <linux/iommu.h>
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#include <linux/errno.h>
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#include <linux/list.h>
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#include <linux/memblock.h>
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#include <linux/export.h>
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#include <asm/cacheflush.h>
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#include <asm/pgtable.h>
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typedef u32 sysmmu_iova_t;
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typedef u32 sysmmu_pte_t;
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/* We does not consider super section mapping (16MB) */
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#define SECT_ORDER 20
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#define LPAGE_ORDER 16
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#define SPAGE_ORDER 12
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#define SECT_SIZE (1 << SECT_ORDER)
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#define LPAGE_SIZE (1 << LPAGE_ORDER)
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#define SPAGE_SIZE (1 << SPAGE_ORDER)
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#define SECT_MASK (~(SECT_SIZE - 1))
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#define LPAGE_MASK (~(LPAGE_SIZE - 1))
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#define SPAGE_MASK (~(SPAGE_SIZE - 1))
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#define lv1ent_fault(sent) ((*(sent) == ZERO_LV2LINK) || \
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((*(sent) & 3) == 0) || ((*(sent) & 3) == 3))
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#define lv1ent_zero(sent) (*(sent) == ZERO_LV2LINK)
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#define lv1ent_page_zero(sent) ((*(sent) & 3) == 1)
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#define lv1ent_page(sent) ((*(sent) != ZERO_LV2LINK) && \
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((*(sent) & 3) == 1))
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#define lv1ent_section(sent) ((*(sent) & 3) == 2)
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#define lv2ent_fault(pent) ((*(pent) & 3) == 0)
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#define lv2ent_small(pent) ((*(pent) & 2) == 2)
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#define lv2ent_large(pent) ((*(pent) & 3) == 1)
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static u32 sysmmu_page_offset(sysmmu_iova_t iova, u32 size)
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{
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return iova & (size - 1);
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}
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#define section_phys(sent) (*(sent) & SECT_MASK)
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#define section_offs(iova) sysmmu_page_offset((iova), SECT_SIZE)
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#define lpage_phys(pent) (*(pent) & LPAGE_MASK)
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#define lpage_offs(iova) sysmmu_page_offset((iova), LPAGE_SIZE)
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#define spage_phys(pent) (*(pent) & SPAGE_MASK)
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#define spage_offs(iova) sysmmu_page_offset((iova), SPAGE_SIZE)
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#define NUM_LV1ENTRIES 4096
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#define NUM_LV2ENTRIES (SECT_SIZE / SPAGE_SIZE)
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static u32 lv1ent_offset(sysmmu_iova_t iova)
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{
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return iova >> SECT_ORDER;
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}
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static u32 lv2ent_offset(sysmmu_iova_t iova)
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{
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return (iova >> SPAGE_ORDER) & (NUM_LV2ENTRIES - 1);
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}
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#define LV2TABLE_SIZE (NUM_LV2ENTRIES * sizeof(sysmmu_pte_t))
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#define SPAGES_PER_LPAGE (LPAGE_SIZE / SPAGE_SIZE)
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#define lv2table_base(sent) (*(sent) & 0xFFFFFC00)
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#define mk_lv1ent_sect(pa) ((pa) | 2)
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#define mk_lv1ent_page(pa) ((pa) | 1)
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#define mk_lv2ent_lpage(pa) ((pa) | 1)
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#define mk_lv2ent_spage(pa) ((pa) | 2)
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#define CTRL_ENABLE 0x5
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#define CTRL_BLOCK 0x7
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#define CTRL_DISABLE 0x0
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#define CFG_LRU 0x1
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#define CFG_QOS(n) ((n & 0xF) << 7)
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#define CFG_MASK 0x0150FFFF /* Selecting bit 0-15, 20, 22 and 24 */
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#define CFG_ACGEN (1 << 24) /* System MMU 3.3 only */
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#define CFG_SYSSEL (1 << 22) /* System MMU 3.2 only */
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#define CFG_FLPDCACHE (1 << 20) /* System MMU 3.2+ only */
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#define REG_MMU_CTRL 0x000
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#define REG_MMU_CFG 0x004
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#define REG_MMU_STATUS 0x008
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#define REG_MMU_FLUSH 0x00C
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#define REG_MMU_FLUSH_ENTRY 0x010
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#define REG_PT_BASE_ADDR 0x014
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#define REG_INT_STATUS 0x018
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#define REG_INT_CLEAR 0x01C
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#define REG_PAGE_FAULT_ADDR 0x024
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#define REG_AW_FAULT_ADDR 0x028
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#define REG_AR_FAULT_ADDR 0x02C
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#define REG_DEFAULT_SLAVE_ADDR 0x030
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#define REG_MMU_VERSION 0x034
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#define MMU_MAJ_VER(val) ((val) >> 7)
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#define MMU_MIN_VER(val) ((val) & 0x7F)
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#define MMU_RAW_VER(reg) (((reg) >> 21) & ((1 << 11) - 1)) /* 11 bits */
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#define MAKE_MMU_VER(maj, min) ((((maj) & 0xF) << 7) | ((min) & 0x7F))
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#define REG_PB0_SADDR 0x04C
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#define REG_PB0_EADDR 0x050
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#define REG_PB1_SADDR 0x054
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#define REG_PB1_EADDR 0x058
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#define has_sysmmu(dev) (dev->archdata.iommu != NULL)
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static struct kmem_cache *lv2table_kmem_cache;
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static sysmmu_pte_t *zero_lv2_table;
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#define ZERO_LV2LINK mk_lv1ent_page(virt_to_phys(zero_lv2_table))
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static sysmmu_pte_t *section_entry(sysmmu_pte_t *pgtable, sysmmu_iova_t iova)
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{
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return pgtable + lv1ent_offset(iova);
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}
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static sysmmu_pte_t *page_entry(sysmmu_pte_t *sent, sysmmu_iova_t iova)
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{
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return (sysmmu_pte_t *)phys_to_virt(
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lv2table_base(sent)) + lv2ent_offset(iova);
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}
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enum exynos_sysmmu_inttype {
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SYSMMU_PAGEFAULT,
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SYSMMU_AR_MULTIHIT,
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SYSMMU_AW_MULTIHIT,
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SYSMMU_BUSERROR,
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SYSMMU_AR_SECURITY,
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SYSMMU_AR_ACCESS,
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SYSMMU_AW_SECURITY,
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SYSMMU_AW_PROTECTION, /* 7 */
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SYSMMU_FAULT_UNKNOWN,
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SYSMMU_FAULTS_NUM
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};
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static unsigned short fault_reg_offset[SYSMMU_FAULTS_NUM] = {
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REG_PAGE_FAULT_ADDR,
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REG_AR_FAULT_ADDR,
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REG_AW_FAULT_ADDR,
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REG_DEFAULT_SLAVE_ADDR,
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REG_AR_FAULT_ADDR,
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REG_AR_FAULT_ADDR,
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REG_AW_FAULT_ADDR,
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REG_AW_FAULT_ADDR
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};
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static char *sysmmu_fault_name[SYSMMU_FAULTS_NUM] = {
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"PAGE FAULT",
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"AR MULTI-HIT FAULT",
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"AW MULTI-HIT FAULT",
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"BUS ERROR",
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"AR SECURITY PROTECTION FAULT",
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"AR ACCESS PROTECTION FAULT",
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"AW SECURITY PROTECTION FAULT",
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"AW ACCESS PROTECTION FAULT",
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"UNKNOWN FAULT"
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};
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/* attached to dev.archdata.iommu of the master device */
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struct exynos_iommu_owner {
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struct list_head client; /* entry of exynos_iommu_domain.clients */
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struct device *dev;
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struct device *sysmmu;
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struct iommu_domain *domain;
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void *vmm_data; /* IO virtual memory manager's data */
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spinlock_t lock; /* Lock to preserve consistency of System MMU */
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};
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struct exynos_iommu_domain {
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struct list_head clients; /* list of sysmmu_drvdata.node */
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sysmmu_pte_t *pgtable; /* lv1 page table, 16KB */
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short *lv2entcnt; /* free lv2 entry counter for each section */
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spinlock_t lock; /* lock for this structure */
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spinlock_t pgtablelock; /* lock for modifying page table @ pgtable */
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};
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struct sysmmu_drvdata {
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struct device *sysmmu; /* System MMU's device descriptor */
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struct device *master; /* Owner of system MMU */
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void __iomem *sfrbase;
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struct clk *clk;
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struct clk *clk_master;
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int activations;
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spinlock_t lock;
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struct iommu_domain *domain;
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phys_addr_t pgtable;
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};
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static bool set_sysmmu_active(struct sysmmu_drvdata *data)
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{
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/* return true if the System MMU was not active previously
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and it needs to be initialized */
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return ++data->activations == 1;
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}
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static bool set_sysmmu_inactive(struct sysmmu_drvdata *data)
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{
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/* return true if the System MMU is needed to be disabled */
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BUG_ON(data->activations < 1);
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return --data->activations == 0;
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}
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static bool is_sysmmu_active(struct sysmmu_drvdata *data)
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{
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return data->activations > 0;
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}
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static void sysmmu_unblock(void __iomem *sfrbase)
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{
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__raw_writel(CTRL_ENABLE, sfrbase + REG_MMU_CTRL);
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}
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static unsigned int __raw_sysmmu_version(struct sysmmu_drvdata *data)
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{
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return MMU_RAW_VER(__raw_readl(data->sfrbase + REG_MMU_VERSION));
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}
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static bool sysmmu_block(void __iomem *sfrbase)
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{
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int i = 120;
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__raw_writel(CTRL_BLOCK, sfrbase + REG_MMU_CTRL);
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while ((i > 0) && !(__raw_readl(sfrbase + REG_MMU_STATUS) & 1))
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--i;
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if (!(__raw_readl(sfrbase + REG_MMU_STATUS) & 1)) {
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sysmmu_unblock(sfrbase);
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return false;
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}
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return true;
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}
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static void __sysmmu_tlb_invalidate(void __iomem *sfrbase)
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{
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__raw_writel(0x1, sfrbase + REG_MMU_FLUSH);
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}
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static void __sysmmu_tlb_invalidate_entry(void __iomem *sfrbase,
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sysmmu_iova_t iova, unsigned int num_inv)
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{
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unsigned int i;
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for (i = 0; i < num_inv; i++) {
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__raw_writel((iova & SPAGE_MASK) | 1,
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sfrbase + REG_MMU_FLUSH_ENTRY);
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iova += SPAGE_SIZE;
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}
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}
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static void __sysmmu_set_ptbase(void __iomem *sfrbase,
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phys_addr_t pgd)
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{
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__raw_writel(pgd, sfrbase + REG_PT_BASE_ADDR);
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__sysmmu_tlb_invalidate(sfrbase);
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}
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static void show_fault_information(const char *name,
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enum exynos_sysmmu_inttype itype,
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phys_addr_t pgtable_base, sysmmu_iova_t fault_addr)
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{
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sysmmu_pte_t *ent;
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if ((itype >= SYSMMU_FAULTS_NUM) || (itype < SYSMMU_PAGEFAULT))
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itype = SYSMMU_FAULT_UNKNOWN;
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pr_err("%s occurred at %#x by %s(Page table base: %pa)\n",
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sysmmu_fault_name[itype], fault_addr, name, &pgtable_base);
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ent = section_entry(phys_to_virt(pgtable_base), fault_addr);
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pr_err("\tLv1 entry: %#x\n", *ent);
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if (lv1ent_page(ent)) {
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ent = page_entry(ent, fault_addr);
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pr_err("\t Lv2 entry: %#x\n", *ent);
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}
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}
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static irqreturn_t exynos_sysmmu_irq(int irq, void *dev_id)
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{
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/* SYSMMU is in blocked when interrupt occurred. */
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struct sysmmu_drvdata *data = dev_id;
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enum exynos_sysmmu_inttype itype;
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sysmmu_iova_t addr = -1;
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int ret = -ENOSYS;
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WARN_ON(!is_sysmmu_active(data));
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spin_lock(&data->lock);
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if (!IS_ERR(data->clk_master))
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clk_enable(data->clk_master);
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itype = (enum exynos_sysmmu_inttype)
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__ffs(__raw_readl(data->sfrbase + REG_INT_STATUS));
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if (WARN_ON(!((itype >= 0) && (itype < SYSMMU_FAULT_UNKNOWN))))
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itype = SYSMMU_FAULT_UNKNOWN;
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else
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addr = __raw_readl(data->sfrbase + fault_reg_offset[itype]);
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if (itype == SYSMMU_FAULT_UNKNOWN) {
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pr_err("%s: Fault is not occurred by System MMU '%s'!\n",
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__func__, dev_name(data->sysmmu));
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pr_err("%s: Please check if IRQ is correctly configured.\n",
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__func__);
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BUG();
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} else {
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unsigned int base =
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__raw_readl(data->sfrbase + REG_PT_BASE_ADDR);
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show_fault_information(dev_name(data->sysmmu),
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itype, base, addr);
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if (data->domain)
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ret = report_iommu_fault(data->domain,
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data->master, addr, itype);
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}
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/* fault is not recovered by fault handler */
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BUG_ON(ret != 0);
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__raw_writel(1 << itype, data->sfrbase + REG_INT_CLEAR);
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sysmmu_unblock(data->sfrbase);
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if (!IS_ERR(data->clk_master))
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clk_disable(data->clk_master);
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spin_unlock(&data->lock);
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return IRQ_HANDLED;
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}
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static void __sysmmu_disable_nocount(struct sysmmu_drvdata *data)
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{
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if (!IS_ERR(data->clk_master))
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clk_enable(data->clk_master);
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__raw_writel(CTRL_DISABLE, data->sfrbase + REG_MMU_CTRL);
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__raw_writel(0, data->sfrbase + REG_MMU_CFG);
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clk_disable(data->clk);
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if (!IS_ERR(data->clk_master))
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clk_disable(data->clk_master);
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}
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static bool __sysmmu_disable(struct sysmmu_drvdata *data)
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{
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bool disabled;
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unsigned long flags;
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spin_lock_irqsave(&data->lock, flags);
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disabled = set_sysmmu_inactive(data);
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if (disabled) {
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data->pgtable = 0;
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data->domain = NULL;
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__sysmmu_disable_nocount(data);
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dev_dbg(data->sysmmu, "Disabled\n");
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} else {
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dev_dbg(data->sysmmu, "%d times left to disable\n",
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data->activations);
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}
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spin_unlock_irqrestore(&data->lock, flags);
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return disabled;
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}
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static void __sysmmu_init_config(struct sysmmu_drvdata *data)
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{
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unsigned int cfg = CFG_LRU | CFG_QOS(15);
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unsigned int ver;
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ver = __raw_sysmmu_version(data);
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if (MMU_MAJ_VER(ver) == 3) {
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if (MMU_MIN_VER(ver) >= 2) {
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cfg |= CFG_FLPDCACHE;
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if (MMU_MIN_VER(ver) == 3) {
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cfg |= CFG_ACGEN;
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cfg &= ~CFG_LRU;
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} else {
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cfg |= CFG_SYSSEL;
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}
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}
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}
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__raw_writel(cfg, data->sfrbase + REG_MMU_CFG);
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}
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static void __sysmmu_enable_nocount(struct sysmmu_drvdata *data)
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{
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if (!IS_ERR(data->clk_master))
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clk_enable(data->clk_master);
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clk_enable(data->clk);
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__raw_writel(CTRL_BLOCK, data->sfrbase + REG_MMU_CTRL);
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__sysmmu_init_config(data);
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__sysmmu_set_ptbase(data->sfrbase, data->pgtable);
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__raw_writel(CTRL_ENABLE, data->sfrbase + REG_MMU_CTRL);
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if (!IS_ERR(data->clk_master))
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clk_disable(data->clk_master);
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}
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|
|
static int __sysmmu_enable(struct sysmmu_drvdata *data,
|
|
phys_addr_t pgtable, struct iommu_domain *domain)
|
|
{
|
|
int ret = 0;
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&data->lock, flags);
|
|
if (set_sysmmu_active(data)) {
|
|
data->pgtable = pgtable;
|
|
data->domain = domain;
|
|
|
|
__sysmmu_enable_nocount(data);
|
|
|
|
dev_dbg(data->sysmmu, "Enabled\n");
|
|
} else {
|
|
ret = (pgtable == data->pgtable) ? 1 : -EBUSY;
|
|
|
|
dev_dbg(data->sysmmu, "already enabled\n");
|
|
}
|
|
|
|
if (WARN_ON(ret < 0))
|
|
set_sysmmu_inactive(data); /* decrement count */
|
|
|
|
spin_unlock_irqrestore(&data->lock, flags);
|
|
|
|
return ret;
|
|
}
|
|
|
|
/* __exynos_sysmmu_enable: Enables System MMU
|
|
*
|
|
* returns -error if an error occurred and System MMU is not enabled,
|
|
* 0 if the System MMU has been just enabled and 1 if System MMU was already
|
|
* enabled before.
|
|
*/
|
|
static int __exynos_sysmmu_enable(struct device *dev, phys_addr_t pgtable,
|
|
struct iommu_domain *domain)
|
|
{
|
|
int ret = 0;
|
|
unsigned long flags;
|
|
struct exynos_iommu_owner *owner = dev->archdata.iommu;
|
|
struct sysmmu_drvdata *data;
|
|
|
|
BUG_ON(!has_sysmmu(dev));
|
|
|
|
spin_lock_irqsave(&owner->lock, flags);
|
|
|
|
data = dev_get_drvdata(owner->sysmmu);
|
|
|
|
ret = __sysmmu_enable(data, pgtable, domain);
|
|
if (ret >= 0)
|
|
data->master = dev;
|
|
|
|
spin_unlock_irqrestore(&owner->lock, flags);
|
|
|
|
return ret;
|
|
}
|
|
|
|
int exynos_sysmmu_enable(struct device *dev, phys_addr_t pgtable)
|
|
{
|
|
BUG_ON(!memblock_is_memory(pgtable));
|
|
|
|
return __exynos_sysmmu_enable(dev, pgtable, NULL);
|
|
}
|
|
|
|
static bool exynos_sysmmu_disable(struct device *dev)
|
|
{
|
|
unsigned long flags;
|
|
bool disabled = true;
|
|
struct exynos_iommu_owner *owner = dev->archdata.iommu;
|
|
struct sysmmu_drvdata *data;
|
|
|
|
BUG_ON(!has_sysmmu(dev));
|
|
|
|
spin_lock_irqsave(&owner->lock, flags);
|
|
|
|
data = dev_get_drvdata(owner->sysmmu);
|
|
|
|
disabled = __sysmmu_disable(data);
|
|
if (disabled)
|
|
data->master = NULL;
|
|
|
|
spin_unlock_irqrestore(&owner->lock, flags);
|
|
|
|
return disabled;
|
|
}
|
|
|
|
static void __sysmmu_tlb_invalidate_flpdcache(struct sysmmu_drvdata *data,
|
|
sysmmu_iova_t iova)
|
|
{
|
|
if (__raw_sysmmu_version(data) == MAKE_MMU_VER(3, 3))
|
|
__raw_writel(iova | 0x1, data->sfrbase + REG_MMU_FLUSH_ENTRY);
|
|
}
|
|
|
|
static void sysmmu_tlb_invalidate_flpdcache(struct device *dev,
|
|
sysmmu_iova_t iova)
|
|
{
|
|
unsigned long flags;
|
|
struct exynos_iommu_owner *owner = dev->archdata.iommu;
|
|
struct sysmmu_drvdata *data = dev_get_drvdata(owner->sysmmu);
|
|
|
|
if (!IS_ERR(data->clk_master))
|
|
clk_enable(data->clk_master);
|
|
|
|
spin_lock_irqsave(&data->lock, flags);
|
|
if (is_sysmmu_active(data))
|
|
__sysmmu_tlb_invalidate_flpdcache(data, iova);
|
|
spin_unlock_irqrestore(&data->lock, flags);
|
|
|
|
if (!IS_ERR(data->clk_master))
|
|
clk_disable(data->clk_master);
|
|
}
|
|
|
|
static void sysmmu_tlb_invalidate_entry(struct device *dev, sysmmu_iova_t iova,
|
|
size_t size)
|
|
{
|
|
struct exynos_iommu_owner *owner = dev->archdata.iommu;
|
|
unsigned long flags;
|
|
struct sysmmu_drvdata *data;
|
|
|
|
data = dev_get_drvdata(owner->sysmmu);
|
|
|
|
spin_lock_irqsave(&data->lock, flags);
|
|
if (is_sysmmu_active(data)) {
|
|
unsigned int num_inv = 1;
|
|
|
|
if (!IS_ERR(data->clk_master))
|
|
clk_enable(data->clk_master);
|
|
|
|
/*
|
|
* L2TLB invalidation required
|
|
* 4KB page: 1 invalidation
|
|
* 64KB page: 16 invalidation
|
|
* 1MB page: 64 invalidation
|
|
* because it is set-associative TLB
|
|
* with 8-way and 64 sets.
|
|
* 1MB page can be cached in one of all sets.
|
|
* 64KB page can be one of 16 consecutive sets.
|
|
*/
|
|
if (MMU_MAJ_VER(__raw_sysmmu_version(data)) == 2)
|
|
num_inv = min_t(unsigned int, size / PAGE_SIZE, 64);
|
|
|
|
if (sysmmu_block(data->sfrbase)) {
|
|
__sysmmu_tlb_invalidate_entry(
|
|
data->sfrbase, iova, num_inv);
|
|
sysmmu_unblock(data->sfrbase);
|
|
}
|
|
if (!IS_ERR(data->clk_master))
|
|
clk_disable(data->clk_master);
|
|
} else {
|
|
dev_dbg(dev, "disabled. Skipping TLB invalidation @ %#x\n",
|
|
iova);
|
|
}
|
|
spin_unlock_irqrestore(&data->lock, flags);
|
|
}
|
|
|
|
void exynos_sysmmu_tlb_invalidate(struct device *dev)
|
|
{
|
|
struct exynos_iommu_owner *owner = dev->archdata.iommu;
|
|
unsigned long flags;
|
|
struct sysmmu_drvdata *data;
|
|
|
|
data = dev_get_drvdata(owner->sysmmu);
|
|
|
|
spin_lock_irqsave(&data->lock, flags);
|
|
if (is_sysmmu_active(data)) {
|
|
if (!IS_ERR(data->clk_master))
|
|
clk_enable(data->clk_master);
|
|
if (sysmmu_block(data->sfrbase)) {
|
|
__sysmmu_tlb_invalidate(data->sfrbase);
|
|
sysmmu_unblock(data->sfrbase);
|
|
}
|
|
if (!IS_ERR(data->clk_master))
|
|
clk_disable(data->clk_master);
|
|
} else {
|
|
dev_dbg(dev, "disabled. Skipping TLB invalidation\n");
|
|
}
|
|
spin_unlock_irqrestore(&data->lock, flags);
|
|
}
|
|
|
|
static int __init exynos_sysmmu_probe(struct platform_device *pdev)
|
|
{
|
|
int irq, ret;
|
|
struct device *dev = &pdev->dev;
|
|
struct sysmmu_drvdata *data;
|
|
struct resource *res;
|
|
|
|
data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
|
|
if (!data)
|
|
return -ENOMEM;
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
data->sfrbase = devm_ioremap_resource(dev, res);
|
|
if (IS_ERR(data->sfrbase))
|
|
return PTR_ERR(data->sfrbase);
|
|
|
|
irq = platform_get_irq(pdev, 0);
|
|
if (irq <= 0) {
|
|
dev_err(dev, "Unable to find IRQ resource\n");
|
|
return irq;
|
|
}
|
|
|
|
ret = devm_request_irq(dev, irq, exynos_sysmmu_irq, 0,
|
|
dev_name(dev), data);
|
|
if (ret) {
|
|
dev_err(dev, "Unabled to register handler of irq %d\n", irq);
|
|
return ret;
|
|
}
|
|
|
|
data->clk = devm_clk_get(dev, "sysmmu");
|
|
if (IS_ERR(data->clk)) {
|
|
dev_err(dev, "Failed to get clock!\n");
|
|
return PTR_ERR(data->clk);
|
|
} else {
|
|
ret = clk_prepare(data->clk);
|
|
if (ret) {
|
|
dev_err(dev, "Failed to prepare clk\n");
|
|
return ret;
|
|
}
|
|
}
|
|
|
|
data->clk_master = devm_clk_get(dev, "master");
|
|
if (!IS_ERR(data->clk_master)) {
|
|
ret = clk_prepare(data->clk_master);
|
|
if (ret) {
|
|
clk_unprepare(data->clk);
|
|
dev_err(dev, "Failed to prepare master's clk\n");
|
|
return ret;
|
|
}
|
|
}
|
|
|
|
data->sysmmu = dev;
|
|
spin_lock_init(&data->lock);
|
|
|
|
platform_set_drvdata(pdev, data);
|
|
|
|
pm_runtime_enable(dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct of_device_id sysmmu_of_match[] __initconst = {
|
|
{ .compatible = "samsung,exynos-sysmmu", },
|
|
{ },
|
|
};
|
|
|
|
static struct platform_driver exynos_sysmmu_driver __refdata = {
|
|
.probe = exynos_sysmmu_probe,
|
|
.driver = {
|
|
.owner = THIS_MODULE,
|
|
.name = "exynos-sysmmu",
|
|
.of_match_table = sysmmu_of_match,
|
|
}
|
|
};
|
|
|
|
static inline void pgtable_flush(void *vastart, void *vaend)
|
|
{
|
|
dmac_flush_range(vastart, vaend);
|
|
outer_flush_range(virt_to_phys(vastart),
|
|
virt_to_phys(vaend));
|
|
}
|
|
|
|
static int exynos_iommu_domain_init(struct iommu_domain *domain)
|
|
{
|
|
struct exynos_iommu_domain *priv;
|
|
int i;
|
|
|
|
priv = kzalloc(sizeof(*priv), GFP_KERNEL);
|
|
if (!priv)
|
|
return -ENOMEM;
|
|
|
|
priv->pgtable = (sysmmu_pte_t *)__get_free_pages(GFP_KERNEL, 2);
|
|
if (!priv->pgtable)
|
|
goto err_pgtable;
|
|
|
|
priv->lv2entcnt = (short *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, 1);
|
|
if (!priv->lv2entcnt)
|
|
goto err_counter;
|
|
|
|
/* w/a of System MMU v3.3 to prevent caching 1MiB mapping */
|
|
for (i = 0; i < NUM_LV1ENTRIES; i += 8) {
|
|
priv->pgtable[i + 0] = ZERO_LV2LINK;
|
|
priv->pgtable[i + 1] = ZERO_LV2LINK;
|
|
priv->pgtable[i + 2] = ZERO_LV2LINK;
|
|
priv->pgtable[i + 3] = ZERO_LV2LINK;
|
|
priv->pgtable[i + 4] = ZERO_LV2LINK;
|
|
priv->pgtable[i + 5] = ZERO_LV2LINK;
|
|
priv->pgtable[i + 6] = ZERO_LV2LINK;
|
|
priv->pgtable[i + 7] = ZERO_LV2LINK;
|
|
}
|
|
|
|
pgtable_flush(priv->pgtable, priv->pgtable + NUM_LV1ENTRIES);
|
|
|
|
spin_lock_init(&priv->lock);
|
|
spin_lock_init(&priv->pgtablelock);
|
|
INIT_LIST_HEAD(&priv->clients);
|
|
|
|
domain->geometry.aperture_start = 0;
|
|
domain->geometry.aperture_end = ~0UL;
|
|
domain->geometry.force_aperture = true;
|
|
|
|
domain->priv = priv;
|
|
return 0;
|
|
|
|
err_counter:
|
|
free_pages((unsigned long)priv->pgtable, 2);
|
|
err_pgtable:
|
|
kfree(priv);
|
|
return -ENOMEM;
|
|
}
|
|
|
|
static void exynos_iommu_domain_destroy(struct iommu_domain *domain)
|
|
{
|
|
struct exynos_iommu_domain *priv = domain->priv;
|
|
struct exynos_iommu_owner *owner;
|
|
unsigned long flags;
|
|
int i;
|
|
|
|
WARN_ON(!list_empty(&priv->clients));
|
|
|
|
spin_lock_irqsave(&priv->lock, flags);
|
|
|
|
list_for_each_entry(owner, &priv->clients, client) {
|
|
while (!exynos_sysmmu_disable(owner->dev))
|
|
; /* until System MMU is actually disabled */
|
|
}
|
|
|
|
while (!list_empty(&priv->clients))
|
|
list_del_init(priv->clients.next);
|
|
|
|
spin_unlock_irqrestore(&priv->lock, flags);
|
|
|
|
for (i = 0; i < NUM_LV1ENTRIES; i++)
|
|
if (lv1ent_page(priv->pgtable + i))
|
|
kmem_cache_free(lv2table_kmem_cache,
|
|
phys_to_virt(lv2table_base(priv->pgtable + i)));
|
|
|
|
free_pages((unsigned long)priv->pgtable, 2);
|
|
free_pages((unsigned long)priv->lv2entcnt, 1);
|
|
kfree(domain->priv);
|
|
domain->priv = NULL;
|
|
}
|
|
|
|
static int exynos_iommu_attach_device(struct iommu_domain *domain,
|
|
struct device *dev)
|
|
{
|
|
struct exynos_iommu_owner *owner = dev->archdata.iommu;
|
|
struct exynos_iommu_domain *priv = domain->priv;
|
|
phys_addr_t pagetable = virt_to_phys(priv->pgtable);
|
|
unsigned long flags;
|
|
int ret;
|
|
|
|
spin_lock_irqsave(&priv->lock, flags);
|
|
|
|
ret = __exynos_sysmmu_enable(dev, pagetable, domain);
|
|
if (ret == 0) {
|
|
list_add_tail(&owner->client, &priv->clients);
|
|
owner->domain = domain;
|
|
}
|
|
|
|
spin_unlock_irqrestore(&priv->lock, flags);
|
|
|
|
if (ret < 0) {
|
|
dev_err(dev, "%s: Failed to attach IOMMU with pgtable %pa\n",
|
|
__func__, &pagetable);
|
|
return ret;
|
|
}
|
|
|
|
dev_dbg(dev, "%s: Attached IOMMU with pgtable %pa %s\n",
|
|
__func__, &pagetable, (ret == 0) ? "" : ", again");
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void exynos_iommu_detach_device(struct iommu_domain *domain,
|
|
struct device *dev)
|
|
{
|
|
struct exynos_iommu_owner *owner;
|
|
struct exynos_iommu_domain *priv = domain->priv;
|
|
phys_addr_t pagetable = virt_to_phys(priv->pgtable);
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&priv->lock, flags);
|
|
|
|
list_for_each_entry(owner, &priv->clients, client) {
|
|
if (owner == dev->archdata.iommu) {
|
|
if (exynos_sysmmu_disable(dev)) {
|
|
list_del_init(&owner->client);
|
|
owner->domain = NULL;
|
|
}
|
|
break;
|
|
}
|
|
}
|
|
|
|
spin_unlock_irqrestore(&priv->lock, flags);
|
|
|
|
if (owner == dev->archdata.iommu)
|
|
dev_dbg(dev, "%s: Detached IOMMU with pgtable %pa\n",
|
|
__func__, &pagetable);
|
|
else
|
|
dev_err(dev, "%s: No IOMMU is attached\n", __func__);
|
|
}
|
|
|
|
static sysmmu_pte_t *alloc_lv2entry(struct exynos_iommu_domain *priv,
|
|
sysmmu_pte_t *sent, sysmmu_iova_t iova, short *pgcounter)
|
|
{
|
|
if (lv1ent_section(sent)) {
|
|
WARN(1, "Trying mapping on %#08x mapped with 1MiB page", iova);
|
|
return ERR_PTR(-EADDRINUSE);
|
|
}
|
|
|
|
if (lv1ent_fault(sent)) {
|
|
sysmmu_pte_t *pent;
|
|
bool need_flush_flpd_cache = lv1ent_zero(sent);
|
|
|
|
pent = kmem_cache_zalloc(lv2table_kmem_cache, GFP_ATOMIC);
|
|
BUG_ON((unsigned int)pent & (LV2TABLE_SIZE - 1));
|
|
if (!pent)
|
|
return ERR_PTR(-ENOMEM);
|
|
|
|
*sent = mk_lv1ent_page(virt_to_phys(pent));
|
|
*pgcounter = NUM_LV2ENTRIES;
|
|
pgtable_flush(pent, pent + NUM_LV2ENTRIES);
|
|
pgtable_flush(sent, sent + 1);
|
|
|
|
/*
|
|
* If pretched SLPD is a fault SLPD in zero_l2_table, FLPD cache
|
|
* may caches the address of zero_l2_table. This function
|
|
* replaces the zero_l2_table with new L2 page table to write
|
|
* valid mappings.
|
|
* Accessing the valid area may cause page fault since FLPD
|
|
* cache may still caches zero_l2_table for the valid area
|
|
* instead of new L2 page table that have the mapping
|
|
* information of the valid area
|
|
* Thus any replacement of zero_l2_table with other valid L2
|
|
* page table must involve FLPD cache invalidation for System
|
|
* MMU v3.3.
|
|
* FLPD cache invalidation is performed with TLB invalidation
|
|
* by VPN without blocking. It is safe to invalidate TLB without
|
|
* blocking because the target address of TLB invalidation is
|
|
* not currently mapped.
|
|
*/
|
|
if (need_flush_flpd_cache) {
|
|
struct exynos_iommu_owner *owner;
|
|
spin_lock(&priv->lock);
|
|
list_for_each_entry(owner, &priv->clients, client)
|
|
sysmmu_tlb_invalidate_flpdcache(
|
|
owner->dev, iova);
|
|
spin_unlock(&priv->lock);
|
|
}
|
|
}
|
|
|
|
return page_entry(sent, iova);
|
|
}
|
|
|
|
static int lv1set_section(struct exynos_iommu_domain *priv,
|
|
sysmmu_pte_t *sent, sysmmu_iova_t iova,
|
|
phys_addr_t paddr, short *pgcnt)
|
|
{
|
|
if (lv1ent_section(sent)) {
|
|
WARN(1, "Trying mapping on 1MiB@%#08x that is mapped",
|
|
iova);
|
|
return -EADDRINUSE;
|
|
}
|
|
|
|
if (lv1ent_page(sent)) {
|
|
if (*pgcnt != NUM_LV2ENTRIES) {
|
|
WARN(1, "Trying mapping on 1MiB@%#08x that is mapped",
|
|
iova);
|
|
return -EADDRINUSE;
|
|
}
|
|
|
|
kmem_cache_free(lv2table_kmem_cache, page_entry(sent, 0));
|
|
*pgcnt = 0;
|
|
}
|
|
|
|
*sent = mk_lv1ent_sect(paddr);
|
|
|
|
pgtable_flush(sent, sent + 1);
|
|
|
|
spin_lock(&priv->lock);
|
|
if (lv1ent_page_zero(sent)) {
|
|
struct exynos_iommu_owner *owner;
|
|
/*
|
|
* Flushing FLPD cache in System MMU v3.3 that may cache a FLPD
|
|
* entry by speculative prefetch of SLPD which has no mapping.
|
|
*/
|
|
list_for_each_entry(owner, &priv->clients, client)
|
|
sysmmu_tlb_invalidate_flpdcache(owner->dev, iova);
|
|
}
|
|
spin_unlock(&priv->lock);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int lv2set_page(sysmmu_pte_t *pent, phys_addr_t paddr, size_t size,
|
|
short *pgcnt)
|
|
{
|
|
if (size == SPAGE_SIZE) {
|
|
if (WARN_ON(!lv2ent_fault(pent)))
|
|
return -EADDRINUSE;
|
|
|
|
*pent = mk_lv2ent_spage(paddr);
|
|
pgtable_flush(pent, pent + 1);
|
|
*pgcnt -= 1;
|
|
} else { /* size == LPAGE_SIZE */
|
|
int i;
|
|
for (i = 0; i < SPAGES_PER_LPAGE; i++, pent++) {
|
|
if (WARN_ON(!lv2ent_fault(pent))) {
|
|
if (i > 0)
|
|
memset(pent - i, 0, sizeof(*pent) * i);
|
|
return -EADDRINUSE;
|
|
}
|
|
|
|
*pent = mk_lv2ent_lpage(paddr);
|
|
}
|
|
pgtable_flush(pent - SPAGES_PER_LPAGE, pent);
|
|
*pgcnt -= SPAGES_PER_LPAGE;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* *CAUTION* to the I/O virtual memory managers that support exynos-iommu:
|
|
*
|
|
* System MMU v3.x have an advanced logic to improve address translation
|
|
* performance with caching more page table entries by a page table walk.
|
|
* However, the logic has a bug that caching fault page table entries and System
|
|
* MMU reports page fault if the cached fault entry is hit even though the fault
|
|
* entry is updated to a valid entry after the entry is cached.
|
|
* To prevent caching fault page table entries which may be updated to valid
|
|
* entries later, the virtual memory manager should care about the w/a about the
|
|
* problem. The followings describe w/a.
|
|
*
|
|
* Any two consecutive I/O virtual address regions must have a hole of 128KiB
|
|
* in maximum to prevent misbehavior of System MMU 3.x. (w/a of h/w bug)
|
|
*
|
|
* Precisely, any start address of I/O virtual region must be aligned by
|
|
* the following sizes for System MMU v3.1 and v3.2.
|
|
* System MMU v3.1: 128KiB
|
|
* System MMU v3.2: 256KiB
|
|
*
|
|
* Because System MMU v3.3 caches page table entries more aggressively, it needs
|
|
* more w/a.
|
|
* - Any two consecutive I/O virtual regions must be have a hole of larger size
|
|
* than or equal size to 128KiB.
|
|
* - Start address of an I/O virtual region must be aligned by 128KiB.
|
|
*/
|
|
static int exynos_iommu_map(struct iommu_domain *domain, unsigned long l_iova,
|
|
phys_addr_t paddr, size_t size, int prot)
|
|
{
|
|
struct exynos_iommu_domain *priv = domain->priv;
|
|
sysmmu_pte_t *entry;
|
|
sysmmu_iova_t iova = (sysmmu_iova_t)l_iova;
|
|
unsigned long flags;
|
|
int ret = -ENOMEM;
|
|
|
|
BUG_ON(priv->pgtable == NULL);
|
|
|
|
spin_lock_irqsave(&priv->pgtablelock, flags);
|
|
|
|
entry = section_entry(priv->pgtable, iova);
|
|
|
|
if (size == SECT_SIZE) {
|
|
ret = lv1set_section(priv, entry, iova, paddr,
|
|
&priv->lv2entcnt[lv1ent_offset(iova)]);
|
|
} else {
|
|
sysmmu_pte_t *pent;
|
|
|
|
pent = alloc_lv2entry(priv, entry, iova,
|
|
&priv->lv2entcnt[lv1ent_offset(iova)]);
|
|
|
|
if (IS_ERR(pent))
|
|
ret = PTR_ERR(pent);
|
|
else
|
|
ret = lv2set_page(pent, paddr, size,
|
|
&priv->lv2entcnt[lv1ent_offset(iova)]);
|
|
}
|
|
|
|
if (ret)
|
|
pr_err("%s: Failed(%d) to map %#zx bytes @ %#x\n",
|
|
__func__, ret, size, iova);
|
|
|
|
spin_unlock_irqrestore(&priv->pgtablelock, flags);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void exynos_iommu_tlb_invalidate_entry(struct exynos_iommu_domain *priv,
|
|
sysmmu_iova_t iova, size_t size)
|
|
{
|
|
struct exynos_iommu_owner *owner;
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&priv->lock, flags);
|
|
|
|
list_for_each_entry(owner, &priv->clients, client)
|
|
sysmmu_tlb_invalidate_entry(owner->dev, iova, size);
|
|
|
|
spin_unlock_irqrestore(&priv->lock, flags);
|
|
}
|
|
|
|
static size_t exynos_iommu_unmap(struct iommu_domain *domain,
|
|
unsigned long l_iova, size_t size)
|
|
{
|
|
struct exynos_iommu_domain *priv = domain->priv;
|
|
sysmmu_iova_t iova = (sysmmu_iova_t)l_iova;
|
|
sysmmu_pte_t *ent;
|
|
size_t err_pgsize;
|
|
unsigned long flags;
|
|
|
|
BUG_ON(priv->pgtable == NULL);
|
|
|
|
spin_lock_irqsave(&priv->pgtablelock, flags);
|
|
|
|
ent = section_entry(priv->pgtable, iova);
|
|
|
|
if (lv1ent_section(ent)) {
|
|
if (WARN_ON(size < SECT_SIZE)) {
|
|
err_pgsize = SECT_SIZE;
|
|
goto err;
|
|
}
|
|
|
|
*ent = ZERO_LV2LINK; /* w/a for h/w bug in Sysmem MMU v3.3 */
|
|
pgtable_flush(ent, ent + 1);
|
|
size = SECT_SIZE;
|
|
goto done;
|
|
}
|
|
|
|
if (unlikely(lv1ent_fault(ent))) {
|
|
if (size > SECT_SIZE)
|
|
size = SECT_SIZE;
|
|
goto done;
|
|
}
|
|
|
|
/* lv1ent_page(sent) == true here */
|
|
|
|
ent = page_entry(ent, iova);
|
|
|
|
if (unlikely(lv2ent_fault(ent))) {
|
|
size = SPAGE_SIZE;
|
|
goto done;
|
|
}
|
|
|
|
if (lv2ent_small(ent)) {
|
|
*ent = 0;
|
|
size = SPAGE_SIZE;
|
|
pgtable_flush(ent, ent + 1);
|
|
priv->lv2entcnt[lv1ent_offset(iova)] += 1;
|
|
goto done;
|
|
}
|
|
|
|
/* lv1ent_large(ent) == true here */
|
|
if (WARN_ON(size < LPAGE_SIZE)) {
|
|
err_pgsize = LPAGE_SIZE;
|
|
goto err;
|
|
}
|
|
|
|
memset(ent, 0, sizeof(*ent) * SPAGES_PER_LPAGE);
|
|
pgtable_flush(ent, ent + SPAGES_PER_LPAGE);
|
|
|
|
size = LPAGE_SIZE;
|
|
priv->lv2entcnt[lv1ent_offset(iova)] += SPAGES_PER_LPAGE;
|
|
done:
|
|
spin_unlock_irqrestore(&priv->pgtablelock, flags);
|
|
|
|
exynos_iommu_tlb_invalidate_entry(priv, iova, size);
|
|
|
|
return size;
|
|
err:
|
|
spin_unlock_irqrestore(&priv->pgtablelock, flags);
|
|
|
|
pr_err("%s: Failed: size(%#zx) @ %#x is smaller than page size %#zx\n",
|
|
__func__, size, iova, err_pgsize);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static phys_addr_t exynos_iommu_iova_to_phys(struct iommu_domain *domain,
|
|
dma_addr_t iova)
|
|
{
|
|
struct exynos_iommu_domain *priv = domain->priv;
|
|
sysmmu_pte_t *entry;
|
|
unsigned long flags;
|
|
phys_addr_t phys = 0;
|
|
|
|
spin_lock_irqsave(&priv->pgtablelock, flags);
|
|
|
|
entry = section_entry(priv->pgtable, iova);
|
|
|
|
if (lv1ent_section(entry)) {
|
|
phys = section_phys(entry) + section_offs(iova);
|
|
} else if (lv1ent_page(entry)) {
|
|
entry = page_entry(entry, iova);
|
|
|
|
if (lv2ent_large(entry))
|
|
phys = lpage_phys(entry) + lpage_offs(iova);
|
|
else if (lv2ent_small(entry))
|
|
phys = spage_phys(entry) + spage_offs(iova);
|
|
}
|
|
|
|
spin_unlock_irqrestore(&priv->pgtablelock, flags);
|
|
|
|
return phys;
|
|
}
|
|
|
|
static int exynos_iommu_add_device(struct device *dev)
|
|
{
|
|
struct iommu_group *group;
|
|
int ret;
|
|
|
|
group = iommu_group_get(dev);
|
|
|
|
if (!group) {
|
|
group = iommu_group_alloc();
|
|
if (IS_ERR(group)) {
|
|
dev_err(dev, "Failed to allocate IOMMU group\n");
|
|
return PTR_ERR(group);
|
|
}
|
|
}
|
|
|
|
ret = iommu_group_add_device(group, dev);
|
|
iommu_group_put(group);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void exynos_iommu_remove_device(struct device *dev)
|
|
{
|
|
iommu_group_remove_device(dev);
|
|
}
|
|
|
|
static struct iommu_ops exynos_iommu_ops = {
|
|
.domain_init = &exynos_iommu_domain_init,
|
|
.domain_destroy = &exynos_iommu_domain_destroy,
|
|
.attach_dev = &exynos_iommu_attach_device,
|
|
.detach_dev = &exynos_iommu_detach_device,
|
|
.map = &exynos_iommu_map,
|
|
.unmap = &exynos_iommu_unmap,
|
|
.iova_to_phys = &exynos_iommu_iova_to_phys,
|
|
.add_device = &exynos_iommu_add_device,
|
|
.remove_device = &exynos_iommu_remove_device,
|
|
.pgsize_bitmap = SECT_SIZE | LPAGE_SIZE | SPAGE_SIZE,
|
|
};
|
|
|
|
static int __init exynos_iommu_init(void)
|
|
{
|
|
int ret;
|
|
|
|
lv2table_kmem_cache = kmem_cache_create("exynos-iommu-lv2table",
|
|
LV2TABLE_SIZE, LV2TABLE_SIZE, 0, NULL);
|
|
if (!lv2table_kmem_cache) {
|
|
pr_err("%s: Failed to create kmem cache\n", __func__);
|
|
return -ENOMEM;
|
|
}
|
|
|
|
ret = platform_driver_register(&exynos_sysmmu_driver);
|
|
if (ret) {
|
|
pr_err("%s: Failed to register driver\n", __func__);
|
|
goto err_reg_driver;
|
|
}
|
|
|
|
zero_lv2_table = kmem_cache_zalloc(lv2table_kmem_cache, GFP_KERNEL);
|
|
if (zero_lv2_table == NULL) {
|
|
pr_err("%s: Failed to allocate zero level2 page table\n",
|
|
__func__);
|
|
ret = -ENOMEM;
|
|
goto err_zero_lv2;
|
|
}
|
|
|
|
ret = bus_set_iommu(&platform_bus_type, &exynos_iommu_ops);
|
|
if (ret) {
|
|
pr_err("%s: Failed to register exynos-iommu driver.\n",
|
|
__func__);
|
|
goto err_set_iommu;
|
|
}
|
|
|
|
return 0;
|
|
err_set_iommu:
|
|
kmem_cache_free(lv2table_kmem_cache, zero_lv2_table);
|
|
err_zero_lv2:
|
|
platform_driver_unregister(&exynos_sysmmu_driver);
|
|
err_reg_driver:
|
|
kmem_cache_destroy(lv2table_kmem_cache);
|
|
return ret;
|
|
}
|
|
subsys_initcall(exynos_iommu_init);
|