Andi Kleen 8c16dc047b x86/perf: Avoid warning for Arch LBR without XSAVE ... Some hypervisors support Arch LBR, but without the LBR XSAVE support. The current Arch LBR init code prints a warning when the xsave size (0) is unexpected. Avoid printing the warning for the "no LBR XSAVE" case. Signed-off-by: Andi Kleen <ak@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://lkml.kernel.org/r/20211215204029.150686-1-ak@linux.intel.com		2022-01-18 12:09:49 +01:00
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amd	x86/events/amd/iommu: Remove redundant assignment to variable shift	2021-12-28 21:30:05 +01:00
intel	x86/perf: Avoid warning for Arch LBR without XSAVE	2022-01-18 12:09:49 +01:00
zhaoxin	x86: Fix various typos in comments	2021-03-18 15:31:53 +01:00
core.c	Peter Zijlstra says:	2022-01-12 16:26:58 -08:00
Kconfig	perf/amd/uncore: Allow the driver to be built as a module	2021-08-26 09:14:36 +02:00
Makefile	perf/x86/rapl: Fix RAPL config variable bug	2020-06-02 11:52:56 +02:00
msr.c	perf/x86/msr: Add Sapphire Rapids CPU support	2021-10-15 11:25:26 +02:00
perf_event.h	perf/x86/intel/lbr: Support LBR format V7	2022-01-18 12:09:48 +01:00
probe.c	perf/x86/rapl: Add msr mask support	2021-02-10 14:44:54 +01:00
probe.h	perf/x86/rapl: Add msr mask support	2021-02-10 14:44:54 +01:00
rapl.c	perf/x86/rapl: fix AMD event handling	2022-01-18 12:09:48 +01:00