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![Robert Richter](/assets/img/avatar_default.png)
Many functions carry the enable_per_layer_report argument. This is a bool value indicating the error information contains some location data where the error occurred. This can easily being determined by checking the pos[] array for values. Negative values indicate there is no location available. So if the top layer is negative, the error location is unknown. Just check if the top layer is negative and remove enable_per_layer_report as function argument and also from struct edac_raw_error_desc. [ bp: Reflow comments to 80 columns, while at it. ] Signed-off-by: Robert Richter <rrichter@marvell.com> Signed-off-by: Borislav Petkov <bp@suse.de> Acked-by: Aristeu Rozanski <aris@redhat.com> Link: https://lkml.kernel.org/r/20200123090210.26933-8-rrichter@marvell.com
661 lines
19 KiB
C
661 lines
19 KiB
C
/*
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* Generic EDAC defs
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*
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* Author: Dave Jiang <djiang@mvista.com>
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*
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* 2006-2008 (c) MontaVista Software, Inc. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*
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*/
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#ifndef _LINUX_EDAC_H_
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#define _LINUX_EDAC_H_
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#include <linux/atomic.h>
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#include <linux/device.h>
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#include <linux/completion.h>
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#include <linux/workqueue.h>
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#include <linux/debugfs.h>
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#include <linux/numa.h>
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#define EDAC_DEVICE_NAME_LEN 31
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struct device;
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#define EDAC_OPSTATE_INVAL -1
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#define EDAC_OPSTATE_POLL 0
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#define EDAC_OPSTATE_NMI 1
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#define EDAC_OPSTATE_INT 2
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extern int edac_op_state;
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struct bus_type *edac_get_sysfs_subsys(void);
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int edac_get_report_status(void);
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void edac_set_report_status(int new);
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enum {
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EDAC_REPORTING_ENABLED,
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EDAC_REPORTING_DISABLED,
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EDAC_REPORTING_FORCE
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};
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static inline void opstate_init(void)
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{
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switch (edac_op_state) {
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case EDAC_OPSTATE_POLL:
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case EDAC_OPSTATE_NMI:
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break;
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default:
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edac_op_state = EDAC_OPSTATE_POLL;
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}
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return;
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}
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/* Max length of a DIMM label*/
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#define EDAC_MC_LABEL_LEN 31
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/* Maximum size of the location string */
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#define LOCATION_SIZE 256
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/* Defines the maximum number of labels that can be reported */
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#define EDAC_MAX_LABELS 8
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/* String used to join two or more labels */
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#define OTHER_LABEL " or "
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/**
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* enum dev_type - describe the type of memory DRAM chips used at the stick
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* @DEV_UNKNOWN: Can't be determined, or MC doesn't support detect it
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* @DEV_X1: 1 bit for data
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* @DEV_X2: 2 bits for data
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* @DEV_X4: 4 bits for data
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* @DEV_X8: 8 bits for data
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* @DEV_X16: 16 bits for data
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* @DEV_X32: 32 bits for data
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* @DEV_X64: 64 bits for data
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*
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* Typical values are x4 and x8.
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*/
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enum dev_type {
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DEV_UNKNOWN = 0,
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DEV_X1,
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DEV_X2,
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DEV_X4,
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DEV_X8,
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DEV_X16,
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DEV_X32, /* Do these parts exist? */
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DEV_X64 /* Do these parts exist? */
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};
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#define DEV_FLAG_UNKNOWN BIT(DEV_UNKNOWN)
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#define DEV_FLAG_X1 BIT(DEV_X1)
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#define DEV_FLAG_X2 BIT(DEV_X2)
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#define DEV_FLAG_X4 BIT(DEV_X4)
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#define DEV_FLAG_X8 BIT(DEV_X8)
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#define DEV_FLAG_X16 BIT(DEV_X16)
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#define DEV_FLAG_X32 BIT(DEV_X32)
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#define DEV_FLAG_X64 BIT(DEV_X64)
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/**
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* enum hw_event_mc_err_type - type of the detected error
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*
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* @HW_EVENT_ERR_CORRECTED: Corrected Error - Indicates that an ECC
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* corrected error was detected
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* @HW_EVENT_ERR_UNCORRECTED: Uncorrected Error - Indicates an error that
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* can't be corrected by ECC, but it is not
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* fatal (maybe it is on an unused memory area,
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* or the memory controller could recover from
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* it for example, by re-trying the operation).
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* @HW_EVENT_ERR_DEFERRED: Deferred Error - Indicates an uncorrectable
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* error whose handling is not urgent. This could
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* be due to hardware data poisoning where the
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* system can continue operation until the poisoned
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* data is consumed. Preemptive measures may also
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* be taken, e.g. offlining pages, etc.
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* @HW_EVENT_ERR_FATAL: Fatal Error - Uncorrected error that could not
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* be recovered.
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* @HW_EVENT_ERR_INFO: Informational - The CPER spec defines a forth
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* type of error: informational logs.
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*/
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enum hw_event_mc_err_type {
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HW_EVENT_ERR_CORRECTED,
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HW_EVENT_ERR_UNCORRECTED,
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HW_EVENT_ERR_DEFERRED,
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HW_EVENT_ERR_FATAL,
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HW_EVENT_ERR_INFO,
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};
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static inline char *mc_event_error_type(const unsigned int err_type)
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{
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switch (err_type) {
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case HW_EVENT_ERR_CORRECTED:
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return "Corrected";
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case HW_EVENT_ERR_UNCORRECTED:
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return "Uncorrected";
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case HW_EVENT_ERR_DEFERRED:
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return "Deferred";
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case HW_EVENT_ERR_FATAL:
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return "Fatal";
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default:
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case HW_EVENT_ERR_INFO:
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return "Info";
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}
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}
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/**
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* enum mem_type - memory types. For a more detailed reference, please see
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* http://en.wikipedia.org/wiki/DRAM
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*
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* @MEM_EMPTY: Empty csrow
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* @MEM_RESERVED: Reserved csrow type
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* @MEM_UNKNOWN: Unknown csrow type
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* @MEM_FPM: FPM - Fast Page Mode, used on systems up to 1995.
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* @MEM_EDO: EDO - Extended data out, used on systems up to 1998.
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* @MEM_BEDO: BEDO - Burst Extended data out, an EDO variant.
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* @MEM_SDR: SDR - Single data rate SDRAM
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* http://en.wikipedia.org/wiki/Synchronous_dynamic_random-access_memory
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* They use 3 pins for chip select: Pins 0 and 2 are
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* for rank 0; pins 1 and 3 are for rank 1, if the memory
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* is dual-rank.
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* @MEM_RDR: Registered SDR SDRAM
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* @MEM_DDR: Double data rate SDRAM
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* http://en.wikipedia.org/wiki/DDR_SDRAM
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* @MEM_RDDR: Registered Double data rate SDRAM
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* This is a variant of the DDR memories.
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* A registered memory has a buffer inside it, hiding
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* part of the memory details to the memory controller.
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* @MEM_RMBS: Rambus DRAM, used on a few Pentium III/IV controllers.
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* @MEM_DDR2: DDR2 RAM, as described at JEDEC JESD79-2F.
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* Those memories are labeled as "PC2-" instead of "PC" to
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* differentiate from DDR.
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* @MEM_FB_DDR2: Fully-Buffered DDR2, as described at JEDEC Std No. 205
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* and JESD206.
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* Those memories are accessed per DIMM slot, and not by
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* a chip select signal.
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* @MEM_RDDR2: Registered DDR2 RAM
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* This is a variant of the DDR2 memories.
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* @MEM_XDR: Rambus XDR
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* It is an evolution of the original RAMBUS memories,
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* created to compete with DDR2. Weren't used on any
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* x86 arch, but cell_edac PPC memory controller uses it.
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* @MEM_DDR3: DDR3 RAM
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* @MEM_RDDR3: Registered DDR3 RAM
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* This is a variant of the DDR3 memories.
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* @MEM_LRDDR3: Load-Reduced DDR3 memory.
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* @MEM_DDR4: Unbuffered DDR4 RAM
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* @MEM_RDDR4: Registered DDR4 RAM
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* This is a variant of the DDR4 memories.
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* @MEM_LRDDR4: Load-Reduced DDR4 memory.
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* @MEM_NVDIMM: Non-volatile RAM
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*/
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enum mem_type {
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MEM_EMPTY = 0,
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MEM_RESERVED,
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MEM_UNKNOWN,
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MEM_FPM,
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MEM_EDO,
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MEM_BEDO,
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MEM_SDR,
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MEM_RDR,
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MEM_DDR,
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MEM_RDDR,
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MEM_RMBS,
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MEM_DDR2,
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MEM_FB_DDR2,
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MEM_RDDR2,
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MEM_XDR,
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MEM_DDR3,
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MEM_RDDR3,
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MEM_LRDDR3,
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MEM_DDR4,
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MEM_RDDR4,
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MEM_LRDDR4,
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MEM_NVDIMM,
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};
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#define MEM_FLAG_EMPTY BIT(MEM_EMPTY)
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#define MEM_FLAG_RESERVED BIT(MEM_RESERVED)
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#define MEM_FLAG_UNKNOWN BIT(MEM_UNKNOWN)
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#define MEM_FLAG_FPM BIT(MEM_FPM)
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#define MEM_FLAG_EDO BIT(MEM_EDO)
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#define MEM_FLAG_BEDO BIT(MEM_BEDO)
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#define MEM_FLAG_SDR BIT(MEM_SDR)
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#define MEM_FLAG_RDR BIT(MEM_RDR)
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#define MEM_FLAG_DDR BIT(MEM_DDR)
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#define MEM_FLAG_RDDR BIT(MEM_RDDR)
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#define MEM_FLAG_RMBS BIT(MEM_RMBS)
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#define MEM_FLAG_DDR2 BIT(MEM_DDR2)
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#define MEM_FLAG_FB_DDR2 BIT(MEM_FB_DDR2)
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#define MEM_FLAG_RDDR2 BIT(MEM_RDDR2)
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#define MEM_FLAG_XDR BIT(MEM_XDR)
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#define MEM_FLAG_DDR3 BIT(MEM_DDR3)
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#define MEM_FLAG_RDDR3 BIT(MEM_RDDR3)
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#define MEM_FLAG_DDR4 BIT(MEM_DDR4)
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#define MEM_FLAG_RDDR4 BIT(MEM_RDDR4)
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#define MEM_FLAG_LRDDR4 BIT(MEM_LRDDR4)
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#define MEM_FLAG_NVDIMM BIT(MEM_NVDIMM)
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/**
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* enum edac-type - Error Detection and Correction capabilities and mode
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* @EDAC_UNKNOWN: Unknown if ECC is available
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* @EDAC_NONE: Doesn't support ECC
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* @EDAC_RESERVED: Reserved ECC type
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* @EDAC_PARITY: Detects parity errors
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* @EDAC_EC: Error Checking - no correction
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* @EDAC_SECDED: Single bit error correction, Double detection
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* @EDAC_S2ECD2ED: Chipkill x2 devices - do these exist?
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* @EDAC_S4ECD4ED: Chipkill x4 devices
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* @EDAC_S8ECD8ED: Chipkill x8 devices
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* @EDAC_S16ECD16ED: Chipkill x16 devices
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*/
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enum edac_type {
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EDAC_UNKNOWN = 0,
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EDAC_NONE,
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EDAC_RESERVED,
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EDAC_PARITY,
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EDAC_EC,
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EDAC_SECDED,
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EDAC_S2ECD2ED,
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EDAC_S4ECD4ED,
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EDAC_S8ECD8ED,
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EDAC_S16ECD16ED,
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};
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#define EDAC_FLAG_UNKNOWN BIT(EDAC_UNKNOWN)
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#define EDAC_FLAG_NONE BIT(EDAC_NONE)
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#define EDAC_FLAG_PARITY BIT(EDAC_PARITY)
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#define EDAC_FLAG_EC BIT(EDAC_EC)
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#define EDAC_FLAG_SECDED BIT(EDAC_SECDED)
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#define EDAC_FLAG_S2ECD2ED BIT(EDAC_S2ECD2ED)
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#define EDAC_FLAG_S4ECD4ED BIT(EDAC_S4ECD4ED)
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#define EDAC_FLAG_S8ECD8ED BIT(EDAC_S8ECD8ED)
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#define EDAC_FLAG_S16ECD16ED BIT(EDAC_S16ECD16ED)
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/**
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* enum scrub_type - scrubbing capabilities
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* @SCRUB_UNKNOWN: Unknown if scrubber is available
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* @SCRUB_NONE: No scrubber
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* @SCRUB_SW_PROG: SW progressive (sequential) scrubbing
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* @SCRUB_SW_SRC: Software scrub only errors
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* @SCRUB_SW_PROG_SRC: Progressive software scrub from an error
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* @SCRUB_SW_TUNABLE: Software scrub frequency is tunable
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* @SCRUB_HW_PROG: HW progressive (sequential) scrubbing
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* @SCRUB_HW_SRC: Hardware scrub only errors
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* @SCRUB_HW_PROG_SRC: Progressive hardware scrub from an error
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* @SCRUB_HW_TUNABLE: Hardware scrub frequency is tunable
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*/
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enum scrub_type {
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SCRUB_UNKNOWN = 0,
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SCRUB_NONE,
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SCRUB_SW_PROG,
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SCRUB_SW_SRC,
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SCRUB_SW_PROG_SRC,
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SCRUB_SW_TUNABLE,
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SCRUB_HW_PROG,
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SCRUB_HW_SRC,
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SCRUB_HW_PROG_SRC,
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SCRUB_HW_TUNABLE
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};
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#define SCRUB_FLAG_SW_PROG BIT(SCRUB_SW_PROG)
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#define SCRUB_FLAG_SW_SRC BIT(SCRUB_SW_SRC)
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#define SCRUB_FLAG_SW_PROG_SRC BIT(SCRUB_SW_PROG_SRC)
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#define SCRUB_FLAG_SW_TUN BIT(SCRUB_SW_SCRUB_TUNABLE)
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#define SCRUB_FLAG_HW_PROG BIT(SCRUB_HW_PROG)
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#define SCRUB_FLAG_HW_SRC BIT(SCRUB_HW_SRC)
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#define SCRUB_FLAG_HW_PROG_SRC BIT(SCRUB_HW_PROG_SRC)
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#define SCRUB_FLAG_HW_TUN BIT(SCRUB_HW_TUNABLE)
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/* FIXME - should have notify capabilities: NMI, LOG, PROC, etc */
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/* EDAC internal operation states */
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#define OP_ALLOC 0x100
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#define OP_RUNNING_POLL 0x201
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#define OP_RUNNING_INTERRUPT 0x202
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#define OP_RUNNING_POLL_INTR 0x203
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#define OP_OFFLINE 0x300
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/**
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* enum edac_mc_layer - memory controller hierarchy layer
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*
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* @EDAC_MC_LAYER_BRANCH: memory layer is named "branch"
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* @EDAC_MC_LAYER_CHANNEL: memory layer is named "channel"
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* @EDAC_MC_LAYER_SLOT: memory layer is named "slot"
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* @EDAC_MC_LAYER_CHIP_SELECT: memory layer is named "chip select"
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* @EDAC_MC_LAYER_ALL_MEM: memory layout is unknown. All memory is mapped
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* as a single memory area. This is used when
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* retrieving errors from a firmware driven driver.
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*
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* This enum is used by the drivers to tell edac_mc_sysfs what name should
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* be used when describing a memory stick location.
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*/
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enum edac_mc_layer_type {
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EDAC_MC_LAYER_BRANCH,
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EDAC_MC_LAYER_CHANNEL,
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EDAC_MC_LAYER_SLOT,
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EDAC_MC_LAYER_CHIP_SELECT,
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EDAC_MC_LAYER_ALL_MEM,
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};
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/**
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* struct edac_mc_layer - describes the memory controller hierarchy
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* @type: layer type
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* @size: number of components per layer. For example,
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* if the channel layer has two channels, size = 2
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* @is_virt_csrow: This layer is part of the "csrow" when old API
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* compatibility mode is enabled. Otherwise, it is
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* a channel
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*/
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struct edac_mc_layer {
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enum edac_mc_layer_type type;
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unsigned size;
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bool is_virt_csrow;
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};
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/*
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* Maximum number of layers used by the memory controller to uniquely
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* identify a single memory stick.
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* NOTE: Changing this constant requires not only to change the constant
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* below, but also to change the existing code at the core, as there are
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* some code there that are optimized for 3 layers.
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*/
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#define EDAC_MAX_LAYERS 3
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struct dimm_info {
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struct device dev;
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char label[EDAC_MC_LABEL_LEN + 1]; /* DIMM label on motherboard */
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/* Memory location data */
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unsigned int location[EDAC_MAX_LAYERS];
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struct mem_ctl_info *mci; /* the parent */
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unsigned int idx; /* index within the parent dimm array */
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u32 grain; /* granularity of reported error in bytes */
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enum dev_type dtype; /* memory device type */
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enum mem_type mtype; /* memory dimm type */
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enum edac_type edac_mode; /* EDAC mode for this dimm */
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u32 nr_pages; /* number of pages on this dimm */
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unsigned int csrow, cschannel; /* Points to the old API data */
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u16 smbios_handle; /* Handle for SMBIOS type 17 */
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};
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/**
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* struct rank_info - contains the information for one DIMM rank
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*
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* @chan_idx: channel number where the rank is (typically, 0 or 1)
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* @ce_count: number of correctable errors for this rank
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* @csrow: A pointer to the chip select row structure (the parent
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* structure). The location of the rank is given by
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* the (csrow->csrow_idx, chan_idx) vector.
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* @dimm: A pointer to the DIMM structure, where the DIMM label
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* information is stored.
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*
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* FIXME: Currently, the EDAC core model will assume one DIMM per rank.
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* This is a bad assumption, but it makes this patch easier. Later
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* patches in this series will fix this issue.
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*/
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struct rank_info {
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int chan_idx;
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struct csrow_info *csrow;
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struct dimm_info *dimm;
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u32 ce_count; /* Correctable Errors for this csrow */
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};
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struct csrow_info {
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struct device dev;
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/* Used only by edac_mc_find_csrow_by_page() */
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unsigned long first_page; /* first page number in csrow */
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unsigned long last_page; /* last page number in csrow */
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unsigned long page_mask; /* used for interleaving -
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* 0UL for non intlv */
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int csrow_idx; /* the chip-select row */
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u32 ue_count; /* Uncorrectable Errors for this csrow */
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u32 ce_count; /* Correctable Errors for this csrow */
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struct mem_ctl_info *mci; /* the parent */
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/* channel information for this csrow */
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u32 nr_channels;
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struct rank_info **channels;
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};
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/*
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* struct errcount_attribute - used to store the several error counts
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*/
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struct errcount_attribute_data {
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int n_layers;
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int pos[EDAC_MAX_LAYERS];
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int layer0, layer1, layer2;
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};
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/**
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* struct edac_raw_error_desc - Raw error report structure
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* @grain: minimum granularity for an error report, in bytes
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* @error_count: number of errors of the same type
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* @type: severity of the error (CE/UE/Fatal)
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* @top_layer: top layer of the error (layer[0])
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* @mid_layer: middle layer of the error (layer[1])
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* @low_layer: low layer of the error (layer[2])
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* @page_frame_number: page where the error happened
|
|
* @offset_in_page: page offset
|
|
* @syndrome: syndrome of the error (or 0 if unknown or if
|
|
* the syndrome is not applicable)
|
|
* @msg: error message
|
|
* @location: location of the error
|
|
* @label: label of the affected DIMM(s)
|
|
* @other_detail: other driver-specific detail about the error
|
|
*/
|
|
struct edac_raw_error_desc {
|
|
char location[LOCATION_SIZE];
|
|
char label[(EDAC_MC_LABEL_LEN + 1 + sizeof(OTHER_LABEL)) * EDAC_MAX_LABELS];
|
|
long grain;
|
|
|
|
u16 error_count;
|
|
enum hw_event_mc_err_type type;
|
|
int top_layer;
|
|
int mid_layer;
|
|
int low_layer;
|
|
unsigned long page_frame_number;
|
|
unsigned long offset_in_page;
|
|
unsigned long syndrome;
|
|
const char *msg;
|
|
const char *other_detail;
|
|
};
|
|
|
|
/* MEMORY controller information structure
|
|
*/
|
|
struct mem_ctl_info {
|
|
struct device dev;
|
|
struct bus_type *bus;
|
|
|
|
struct list_head link; /* for global list of mem_ctl_info structs */
|
|
|
|
struct module *owner; /* Module owner of this control struct */
|
|
|
|
unsigned long mtype_cap; /* memory types supported by mc */
|
|
unsigned long edac_ctl_cap; /* Mem controller EDAC capabilities */
|
|
unsigned long edac_cap; /* configuration capabilities - this is
|
|
* closely related to edac_ctl_cap. The
|
|
* difference is that the controller may be
|
|
* capable of s4ecd4ed which would be listed
|
|
* in edac_ctl_cap, but if channels aren't
|
|
* capable of s4ecd4ed then the edac_cap would
|
|
* not have that capability.
|
|
*/
|
|
unsigned long scrub_cap; /* chipset scrub capabilities */
|
|
enum scrub_type scrub_mode; /* current scrub mode */
|
|
|
|
/* Translates sdram memory scrub rate given in bytes/sec to the
|
|
internal representation and configures whatever else needs
|
|
to be configured.
|
|
*/
|
|
int (*set_sdram_scrub_rate) (struct mem_ctl_info * mci, u32 bw);
|
|
|
|
/* Get the current sdram memory scrub rate from the internal
|
|
representation and converts it to the closest matching
|
|
bandwidth in bytes/sec.
|
|
*/
|
|
int (*get_sdram_scrub_rate) (struct mem_ctl_info * mci);
|
|
|
|
|
|
/* pointer to edac checking routine */
|
|
void (*edac_check) (struct mem_ctl_info * mci);
|
|
|
|
/*
|
|
* Remaps memory pages: controller pages to physical pages.
|
|
* For most MC's, this will be NULL.
|
|
*/
|
|
/* FIXME - why not send the phys page to begin with? */
|
|
unsigned long (*ctl_page_to_phys) (struct mem_ctl_info * mci,
|
|
unsigned long page);
|
|
int mc_idx;
|
|
struct csrow_info **csrows;
|
|
unsigned int nr_csrows, num_cschannel;
|
|
|
|
/*
|
|
* Memory Controller hierarchy
|
|
*
|
|
* There are basically two types of memory controller: the ones that
|
|
* sees memory sticks ("dimms"), and the ones that sees memory ranks.
|
|
* All old memory controllers enumerate memories per rank, but most
|
|
* of the recent drivers enumerate memories per DIMM, instead.
|
|
* When the memory controller is per rank, csbased is true.
|
|
*/
|
|
unsigned int n_layers;
|
|
struct edac_mc_layer *layers;
|
|
bool csbased;
|
|
|
|
/*
|
|
* DIMM info. Will eventually remove the entire csrows_info some day
|
|
*/
|
|
unsigned int tot_dimms;
|
|
struct dimm_info **dimms;
|
|
|
|
/*
|
|
* FIXME - what about controllers on other busses? - IDs must be
|
|
* unique. dev pointer should be sufficiently unique, but
|
|
* BUS:SLOT.FUNC numbers may not be unique.
|
|
*/
|
|
struct device *pdev;
|
|
const char *mod_name;
|
|
const char *ctl_name;
|
|
const char *dev_name;
|
|
void *pvt_info;
|
|
unsigned long start_time; /* mci load start time (in jiffies) */
|
|
|
|
/*
|
|
* drivers shouldn't access those fields directly, as the core
|
|
* already handles that.
|
|
*/
|
|
u32 ce_noinfo_count, ue_noinfo_count;
|
|
u32 ue_mc, ce_mc;
|
|
u32 *ce_per_layer[EDAC_MAX_LAYERS], *ue_per_layer[EDAC_MAX_LAYERS];
|
|
|
|
struct completion complete;
|
|
|
|
/* Additional top controller level attributes, but specified
|
|
* by the low level driver.
|
|
*
|
|
* Set by the low level driver to provide attributes at the
|
|
* controller level.
|
|
* An array of structures, NULL terminated
|
|
*
|
|
* If attributes are desired, then set to array of attributes
|
|
* If no attributes are desired, leave NULL
|
|
*/
|
|
const struct mcidev_sysfs_attribute *mc_driver_sysfs_attributes;
|
|
|
|
/* work struct for this MC */
|
|
struct delayed_work work;
|
|
|
|
/*
|
|
* Used to report an error - by being at the global struct
|
|
* makes the memory allocated by the EDAC core
|
|
*/
|
|
struct edac_raw_error_desc error_desc;
|
|
|
|
/* the internal state of this controller instance */
|
|
int op_state;
|
|
|
|
struct dentry *debugfs;
|
|
u8 fake_inject_layer[EDAC_MAX_LAYERS];
|
|
bool fake_inject_ue;
|
|
u16 fake_inject_count;
|
|
};
|
|
|
|
#define mci_for_each_dimm(mci, dimm) \
|
|
for ((dimm) = (mci)->dimms[0]; \
|
|
(dimm); \
|
|
(dimm) = (dimm)->idx + 1 < (mci)->tot_dimms \
|
|
? (mci)->dimms[(dimm)->idx + 1] \
|
|
: NULL)
|
|
|
|
/**
|
|
* edac_get_dimm_by_index - Get DIMM info at @index from a memory
|
|
* controller
|
|
*
|
|
* @mci: MC descriptor struct mem_ctl_info
|
|
* @index: index in the memory controller's DIMM array
|
|
*
|
|
* Returns a struct dimm_info * or NULL on failure.
|
|
*/
|
|
static inline struct dimm_info *
|
|
edac_get_dimm_by_index(struct mem_ctl_info *mci, int index)
|
|
{
|
|
if (index < 0 || index >= mci->tot_dimms)
|
|
return NULL;
|
|
|
|
if (WARN_ON_ONCE(mci->dimms[index]->idx != index))
|
|
return NULL;
|
|
|
|
return mci->dimms[index];
|
|
}
|
|
|
|
/**
|
|
* edac_get_dimm - Get DIMM info from a memory controller given by
|
|
* [layer0,layer1,layer2] position
|
|
*
|
|
* @mci: MC descriptor struct mem_ctl_info
|
|
* @layer0: layer0 position
|
|
* @layer1: layer1 position. Unused if n_layers < 2
|
|
* @layer2: layer2 position. Unused if n_layers < 3
|
|
*
|
|
* For 1 layer, this function returns "dimms[layer0]";
|
|
*
|
|
* For 2 layers, this function is similar to allocating a two-dimensional
|
|
* array and returning "dimms[layer0][layer1]";
|
|
*
|
|
* For 3 layers, this function is similar to allocating a tri-dimensional
|
|
* array and returning "dimms[layer0][layer1][layer2]";
|
|
*/
|
|
static inline struct dimm_info *edac_get_dimm(struct mem_ctl_info *mci,
|
|
int layer0, int layer1, int layer2)
|
|
{
|
|
int index;
|
|
|
|
if (layer0 < 0
|
|
|| (mci->n_layers > 1 && layer1 < 0)
|
|
|| (mci->n_layers > 2 && layer2 < 0))
|
|
return NULL;
|
|
|
|
index = layer0;
|
|
|
|
if (mci->n_layers > 1)
|
|
index = index * mci->layers[1].size + layer1;
|
|
|
|
if (mci->n_layers > 2)
|
|
index = index * mci->layers[2].size + layer2;
|
|
|
|
return edac_get_dimm_by_index(mci, index);
|
|
}
|
|
#endif /* _LINUX_EDAC_H_ */
|