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![Rafael J. Wysocki](/assets/img/avatar_default.png)
* pm-sleep: PM / sleep: trace_device_pm_callback coverage in dpm_prepare/complete PM / wakeup: add a dummy wakeup_source to record statistics PM / sleep: Make suspend-to-idle-specific code depend on CONFIG_SUSPEND PM / sleep: Return -EBUSY from suspend_enter() on wakeup detection PM / tick: Add tracepoints for suspend-to-idle diagnostics PM / sleep: Fix symbol name in a comment in kernel/power/main.c leds / PM: fix hibernation on arm when gpio-led used with CPU led trigger ARM: omap-device: use SET_NOIRQ_SYSTEM_SLEEP_PM_OPS bus: omap_l3_noc: add missed callbacks for suspend-to-disk PM / sleep: Add macro to define common noirq system PM callbacks PM / sleep: Refine diagnostic messages in enter_state() PM / wakeup: validate wakeup source before activating it. * pm-runtime: PM / Runtime: Update last_busy in rpm_resume PM / runtime: add note about re-calling in during device probe()
377 lines
10 KiB
C
377 lines
10 KiB
C
/*
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* OMAP L3 Interconnect error handling driver
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*
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* Copyright (C) 2011-2015 Texas Instruments Incorporated - http://www.ti.com/
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* Santosh Shilimkar <santosh.shilimkar@ti.com>
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* Sricharan <r.sricharan@ti.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include "omap_l3_noc.h"
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/**
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* l3_handle_target() - Handle Target specific parse and reporting
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* @l3: pointer to l3 struct
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* @base: base address of clkdm
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* @flag_mux: flagmux corresponding to the event
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* @err_src: error source index of the slave (target)
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*
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* This does the second part of the error interrupt handling:
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* 3) Parse in the slave information
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* 4) Print the logged information.
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* 5) Add dump stack to provide kernel trace.
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* 6) Clear the source if known.
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*
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* This handles two types of errors:
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* 1) Custom errors in L3 :
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* Target like DMM/FW/EMIF generates SRESP=ERR error
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* 2) Standard L3 error:
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* - Unsupported CMD.
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* L3 tries to access target while it is idle
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* - OCP disconnect.
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* - Address hole error:
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* If DSS/ISS/FDIF/USBHOSTFS access a target where they
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* do not have connectivity, the error is logged in
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* their default target which is DMM2.
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*
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* On High Secure devices, firewall errors are possible and those
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* can be trapped as well. But the trapping is implemented as part
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* secure software and hence need not be implemented here.
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*/
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static int l3_handle_target(struct omap_l3 *l3, void __iomem *base,
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struct l3_flagmux_data *flag_mux, int err_src)
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{
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int k;
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u32 std_err_main, clear, masterid;
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u8 op_code, m_req_info;
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void __iomem *l3_targ_base;
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void __iomem *l3_targ_stderr, *l3_targ_slvofslsb, *l3_targ_mstaddr;
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void __iomem *l3_targ_hdr, *l3_targ_info;
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struct l3_target_data *l3_targ_inst;
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struct l3_masters_data *master;
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char *target_name, *master_name = "UN IDENTIFIED";
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char *err_description;
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char err_string[30] = { 0 };
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char info_string[60] = { 0 };
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/* We DONOT expect err_src to go out of bounds */
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BUG_ON(err_src > MAX_CLKDM_TARGETS);
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if (err_src < flag_mux->num_targ_data) {
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l3_targ_inst = &flag_mux->l3_targ[err_src];
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target_name = l3_targ_inst->name;
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l3_targ_base = base + l3_targ_inst->offset;
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} else {
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target_name = L3_TARGET_NOT_SUPPORTED;
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}
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if (target_name == L3_TARGET_NOT_SUPPORTED)
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return -ENODEV;
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/* Read the stderrlog_main_source from clk domain */
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l3_targ_stderr = l3_targ_base + L3_TARG_STDERRLOG_MAIN;
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l3_targ_slvofslsb = l3_targ_base + L3_TARG_STDERRLOG_SLVOFSLSB;
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std_err_main = readl_relaxed(l3_targ_stderr);
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switch (std_err_main & CUSTOM_ERROR) {
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case STANDARD_ERROR:
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err_description = "Standard";
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snprintf(err_string, sizeof(err_string),
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": At Address: 0x%08X ",
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readl_relaxed(l3_targ_slvofslsb));
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l3_targ_mstaddr = l3_targ_base + L3_TARG_STDERRLOG_MSTADDR;
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l3_targ_hdr = l3_targ_base + L3_TARG_STDERRLOG_HDR;
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l3_targ_info = l3_targ_base + L3_TARG_STDERRLOG_INFO;
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break;
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case CUSTOM_ERROR:
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err_description = "Custom";
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l3_targ_mstaddr = l3_targ_base +
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L3_TARG_STDERRLOG_CINFO_MSTADDR;
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l3_targ_hdr = l3_targ_base + L3_TARG_STDERRLOG_CINFO_OPCODE;
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l3_targ_info = l3_targ_base + L3_TARG_STDERRLOG_CINFO_INFO;
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break;
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default:
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/* Nothing to be handled here as of now */
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return 0;
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}
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/* STDERRLOG_MSTADDR Stores the NTTP master address. */
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masterid = (readl_relaxed(l3_targ_mstaddr) &
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l3->mst_addr_mask) >> __ffs(l3->mst_addr_mask);
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for (k = 0, master = l3->l3_masters; k < l3->num_masters;
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k++, master++) {
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if (masterid == master->id) {
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master_name = master->name;
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break;
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}
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}
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op_code = readl_relaxed(l3_targ_hdr) & 0x7;
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m_req_info = readl_relaxed(l3_targ_info) & 0xF;
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snprintf(info_string, sizeof(info_string),
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": %s in %s mode during %s access",
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(m_req_info & BIT(0)) ? "Opcode Fetch" : "Data Access",
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(m_req_info & BIT(1)) ? "Supervisor" : "User",
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(m_req_info & BIT(3)) ? "Debug" : "Functional");
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WARN(true,
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"%s:L3 %s Error: MASTER %s TARGET %s (%s)%s%s\n",
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dev_name(l3->dev),
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err_description,
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master_name, target_name,
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l3_transaction_type[op_code],
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err_string, info_string);
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/* clear the std error log*/
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clear = std_err_main | CLEAR_STDERR_LOG;
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writel_relaxed(clear, l3_targ_stderr);
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return 0;
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}
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/**
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* l3_interrupt_handler() - interrupt handler for l3 events
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* @irq: irq number
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* @_l3: pointer to l3 structure
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*
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* Interrupt Handler for L3 error detection.
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* 1) Identify the L3 clockdomain partition to which the error belongs to.
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* 2) Identify the slave where the error information is logged
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* ... handle the slave event..
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* 7) if the slave is unknown, mask out the slave.
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*/
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static irqreturn_t l3_interrupt_handler(int irq, void *_l3)
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{
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struct omap_l3 *l3 = _l3;
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int inttype, i, ret;
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int err_src = 0;
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u32 err_reg, mask_val;
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void __iomem *base, *mask_reg;
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struct l3_flagmux_data *flag_mux;
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/* Get the Type of interrupt */
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inttype = irq == l3->app_irq ? L3_APPLICATION_ERROR : L3_DEBUG_ERROR;
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for (i = 0; i < l3->num_modules; i++) {
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/*
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* Read the regerr register of the clock domain
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* to determine the source
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*/
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base = l3->l3_base[i];
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flag_mux = l3->l3_flagmux[i];
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err_reg = readl_relaxed(base + flag_mux->offset +
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L3_FLAGMUX_REGERR0 + (inttype << 3));
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err_reg &= ~(inttype ? flag_mux->mask_app_bits :
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flag_mux->mask_dbg_bits);
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/* Get the corresponding error and analyse */
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if (err_reg) {
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/* Identify the source from control status register */
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err_src = __ffs(err_reg);
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ret = l3_handle_target(l3, base, flag_mux, err_src);
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/*
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* Certain plaforms may have "undocumented" status
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* pending on boot. So dont generate a severe warning
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* here. Just mask it off to prevent the error from
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* reoccuring and locking up the system.
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*/
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if (ret) {
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dev_err(l3->dev,
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"L3 %s error: target %d mod:%d %s\n",
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inttype ? "debug" : "application",
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err_src, i, "(unclearable)");
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mask_reg = base + flag_mux->offset +
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L3_FLAGMUX_MASK0 + (inttype << 3);
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mask_val = readl_relaxed(mask_reg);
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mask_val &= ~(1 << err_src);
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writel_relaxed(mask_val, mask_reg);
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/* Mark these bits as to be ignored */
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if (inttype)
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flag_mux->mask_app_bits |= 1 << err_src;
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else
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flag_mux->mask_dbg_bits |= 1 << err_src;
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}
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/* Error found so break the for loop */
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return IRQ_HANDLED;
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}
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}
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dev_err(l3->dev, "L3 %s IRQ not handled!!\n",
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inttype ? "debug" : "application");
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return IRQ_NONE;
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}
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static const struct of_device_id l3_noc_match[] = {
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{.compatible = "ti,omap4-l3-noc", .data = &omap4_l3_data},
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{.compatible = "ti,omap5-l3-noc", .data = &omap5_l3_data},
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{.compatible = "ti,dra7-l3-noc", .data = &dra_l3_data},
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{.compatible = "ti,am4372-l3-noc", .data = &am4372_l3_data},
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{},
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};
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MODULE_DEVICE_TABLE(of, l3_noc_match);
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static int omap_l3_probe(struct platform_device *pdev)
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{
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const struct of_device_id *of_id;
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static struct omap_l3 *l3;
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int ret, i, res_idx;
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of_id = of_match_device(l3_noc_match, &pdev->dev);
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if (!of_id) {
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dev_err(&pdev->dev, "OF data missing\n");
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return -EINVAL;
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}
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l3 = devm_kzalloc(&pdev->dev, sizeof(*l3), GFP_KERNEL);
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if (!l3)
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return -ENOMEM;
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memcpy(l3, of_id->data, sizeof(*l3));
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l3->dev = &pdev->dev;
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platform_set_drvdata(pdev, l3);
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/* Get mem resources */
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for (i = 0, res_idx = 0; i < l3->num_modules; i++) {
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struct resource *res;
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if (l3->l3_base[i] == L3_BASE_IS_SUBMODULE) {
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/* First entry cannot be submodule */
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BUG_ON(i == 0);
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l3->l3_base[i] = l3->l3_base[i - 1];
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continue;
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}
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res = platform_get_resource(pdev, IORESOURCE_MEM, res_idx);
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l3->l3_base[i] = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(l3->l3_base[i])) {
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dev_err(l3->dev, "ioremap %d failed\n", i);
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return PTR_ERR(l3->l3_base[i]);
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}
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res_idx++;
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}
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/*
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* Setup interrupt Handlers
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*/
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l3->debug_irq = platform_get_irq(pdev, 0);
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ret = devm_request_irq(l3->dev, l3->debug_irq, l3_interrupt_handler,
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0x0, "l3-dbg-irq", l3);
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if (ret) {
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dev_err(l3->dev, "request_irq failed for %d\n",
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l3->debug_irq);
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return ret;
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}
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l3->app_irq = platform_get_irq(pdev, 1);
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ret = devm_request_irq(l3->dev, l3->app_irq, l3_interrupt_handler,
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0x0, "l3-app-irq", l3);
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if (ret)
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dev_err(l3->dev, "request_irq failed for %d\n", l3->app_irq);
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return ret;
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}
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#ifdef CONFIG_PM_SLEEP
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/**
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* l3_resume_noirq() - resume function for l3_noc
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* @dev: pointer to l3_noc device structure
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*
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* We only have the resume handler only since we
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* have already maintained the delta register
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* configuration as part of configuring the system
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*/
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static int l3_resume_noirq(struct device *dev)
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{
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struct omap_l3 *l3 = dev_get_drvdata(dev);
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int i;
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struct l3_flagmux_data *flag_mux;
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void __iomem *base, *mask_regx = NULL;
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u32 mask_val;
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for (i = 0; i < l3->num_modules; i++) {
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base = l3->l3_base[i];
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flag_mux = l3->l3_flagmux[i];
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if (!flag_mux->mask_app_bits && !flag_mux->mask_dbg_bits)
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continue;
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mask_regx = base + flag_mux->offset + L3_FLAGMUX_MASK0 +
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(L3_APPLICATION_ERROR << 3);
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mask_val = readl_relaxed(mask_regx);
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mask_val &= ~(flag_mux->mask_app_bits);
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writel_relaxed(mask_val, mask_regx);
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mask_regx = base + flag_mux->offset + L3_FLAGMUX_MASK0 +
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(L3_DEBUG_ERROR << 3);
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mask_val = readl_relaxed(mask_regx);
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mask_val &= ~(flag_mux->mask_dbg_bits);
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writel_relaxed(mask_val, mask_regx);
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}
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/* Dummy read to force OCP barrier */
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if (mask_regx)
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(void)readl(mask_regx);
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return 0;
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}
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static const struct dev_pm_ops l3_dev_pm_ops = {
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SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(NULL, l3_resume_noirq)
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};
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#define L3_DEV_PM_OPS (&l3_dev_pm_ops)
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#else
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#define L3_DEV_PM_OPS NULL
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#endif
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static struct platform_driver omap_l3_driver = {
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.probe = omap_l3_probe,
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.driver = {
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.name = "omap_l3_noc",
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.pm = L3_DEV_PM_OPS,
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.of_match_table = of_match_ptr(l3_noc_match),
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},
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};
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static int __init omap_l3_init(void)
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{
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return platform_driver_register(&omap_l3_driver);
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}
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postcore_initcall_sync(omap_l3_init);
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static void __exit omap_l3_exit(void)
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{
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platform_driver_unregister(&omap_l3_driver);
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}
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module_exit(omap_l3_exit);
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