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![Jason Gunthorpe](/assets/img/avatar_default.png)
Requiring contiguous kernel memory is not a good idea, this is a limited resource and allocation can fail under normal work loads. This introduces a .write_sg op that supporting drivers can provide to DMA directly from dis-contiguous memory and a new entry point fpga_mgr_buf_load_sg that users can call to directly provide page lists. The full matrix of compatibility is provided, either the linear or sg interface can be used by the user with a driver supporting either interface. A notable change for drivers is that the .write op can now be called multiple times. Signed-off-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Acked-by: Alan Tull <atull@opensource.altera.com> Acked-by: Moritz Fischer <moritz.fischer@ettus.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
586 lines
15 KiB
C
586 lines
15 KiB
C
/*
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* FPGA Manager Core
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*
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* Copyright (C) 2013-2015 Altera Corporation
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*
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* With code from the mailing list:
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* Copyright (C) 2013 Xilinx, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/firmware.h>
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#include <linux/fpga/fpga-mgr.h>
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#include <linux/idr.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/mutex.h>
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#include <linux/slab.h>
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#include <linux/scatterlist.h>
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#include <linux/highmem.h>
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static DEFINE_IDA(fpga_mgr_ida);
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static struct class *fpga_mgr_class;
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/*
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* Call the low level driver's write_init function. This will do the
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* device-specific things to get the FPGA into the state where it is ready to
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* receive an FPGA image. The low level driver only gets to see the first
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* initial_header_size bytes in the buffer.
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*/
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static int fpga_mgr_write_init_buf(struct fpga_manager *mgr,
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struct fpga_image_info *info,
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const char *buf, size_t count)
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{
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int ret;
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mgr->state = FPGA_MGR_STATE_WRITE_INIT;
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if (!mgr->mops->initial_header_size)
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ret = mgr->mops->write_init(mgr, info, NULL, 0);
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else
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ret = mgr->mops->write_init(
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mgr, info, buf, min(mgr->mops->initial_header_size, count));
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if (ret) {
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dev_err(&mgr->dev, "Error preparing FPGA for writing\n");
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mgr->state = FPGA_MGR_STATE_WRITE_INIT_ERR;
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return ret;
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}
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return 0;
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}
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static int fpga_mgr_write_init_sg(struct fpga_manager *mgr,
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struct fpga_image_info *info,
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struct sg_table *sgt)
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{
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struct sg_mapping_iter miter;
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size_t len;
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char *buf;
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int ret;
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if (!mgr->mops->initial_header_size)
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return fpga_mgr_write_init_buf(mgr, info, NULL, 0);
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/*
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* First try to use miter to map the first fragment to access the
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* header, this is the typical path.
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*/
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sg_miter_start(&miter, sgt->sgl, sgt->nents, SG_MITER_FROM_SG);
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if (sg_miter_next(&miter) &&
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miter.length >= mgr->mops->initial_header_size) {
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ret = fpga_mgr_write_init_buf(mgr, info, miter.addr,
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miter.length);
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sg_miter_stop(&miter);
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return ret;
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}
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sg_miter_stop(&miter);
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/* Otherwise copy the fragments into temporary memory. */
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buf = kmalloc(mgr->mops->initial_header_size, GFP_KERNEL);
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if (!buf)
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return -ENOMEM;
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len = sg_copy_to_buffer(sgt->sgl, sgt->nents, buf,
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mgr->mops->initial_header_size);
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ret = fpga_mgr_write_init_buf(mgr, info, buf, len);
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kfree(buf);
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return ret;
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}
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/*
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* After all the FPGA image has been written, do the device specific steps to
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* finish and set the FPGA into operating mode.
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*/
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static int fpga_mgr_write_complete(struct fpga_manager *mgr,
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struct fpga_image_info *info)
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{
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int ret;
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mgr->state = FPGA_MGR_STATE_WRITE_COMPLETE;
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ret = mgr->mops->write_complete(mgr, info);
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if (ret) {
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dev_err(&mgr->dev, "Error after writing image data to FPGA\n");
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mgr->state = FPGA_MGR_STATE_WRITE_COMPLETE_ERR;
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return ret;
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}
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mgr->state = FPGA_MGR_STATE_OPERATING;
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return 0;
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}
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/**
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* fpga_mgr_buf_load_sg - load fpga from image in buffer from a scatter list
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* @mgr: fpga manager
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* @info: fpga image specific information
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* @sgt: scatterlist table
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*
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* Step the low level fpga manager through the device-specific steps of getting
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* an FPGA ready to be configured, writing the image to it, then doing whatever
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* post-configuration steps necessary. This code assumes the caller got the
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* mgr pointer from of_fpga_mgr_get() or fpga_mgr_get() and checked that it is
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* not an error code.
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*
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* This is the preferred entry point for FPGA programming, it does not require
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* any contiguous kernel memory.
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*
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* Return: 0 on success, negative error code otherwise.
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*/
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int fpga_mgr_buf_load_sg(struct fpga_manager *mgr, struct fpga_image_info *info,
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struct sg_table *sgt)
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{
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int ret;
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ret = fpga_mgr_write_init_sg(mgr, info, sgt);
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if (ret)
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return ret;
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/* Write the FPGA image to the FPGA. */
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mgr->state = FPGA_MGR_STATE_WRITE;
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if (mgr->mops->write_sg) {
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ret = mgr->mops->write_sg(mgr, sgt);
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} else {
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struct sg_mapping_iter miter;
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sg_miter_start(&miter, sgt->sgl, sgt->nents, SG_MITER_FROM_SG);
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while (sg_miter_next(&miter)) {
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ret = mgr->mops->write(mgr, miter.addr, miter.length);
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if (ret)
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break;
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}
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sg_miter_stop(&miter);
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}
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if (ret) {
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dev_err(&mgr->dev, "Error while writing image data to FPGA\n");
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mgr->state = FPGA_MGR_STATE_WRITE_ERR;
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return ret;
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}
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return fpga_mgr_write_complete(mgr, info);
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}
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EXPORT_SYMBOL_GPL(fpga_mgr_buf_load_sg);
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static int fpga_mgr_buf_load_mapped(struct fpga_manager *mgr,
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struct fpga_image_info *info,
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const char *buf, size_t count)
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{
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int ret;
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ret = fpga_mgr_write_init_buf(mgr, info, buf, count);
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if (ret)
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return ret;
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/*
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* Write the FPGA image to the FPGA.
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*/
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mgr->state = FPGA_MGR_STATE_WRITE;
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ret = mgr->mops->write(mgr, buf, count);
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if (ret) {
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dev_err(&mgr->dev, "Error while writing image data to FPGA\n");
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mgr->state = FPGA_MGR_STATE_WRITE_ERR;
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return ret;
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}
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return fpga_mgr_write_complete(mgr, info);
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}
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/**
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* fpga_mgr_buf_load - load fpga from image in buffer
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* @mgr: fpga manager
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* @flags: flags setting fpga confuration modes
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* @buf: buffer contain fpga image
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* @count: byte count of buf
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*
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* Step the low level fpga manager through the device-specific steps of getting
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* an FPGA ready to be configured, writing the image to it, then doing whatever
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* post-configuration steps necessary. This code assumes the caller got the
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* mgr pointer from of_fpga_mgr_get() and checked that it is not an error code.
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*
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* Return: 0 on success, negative error code otherwise.
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*/
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int fpga_mgr_buf_load(struct fpga_manager *mgr, struct fpga_image_info *info,
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const char *buf, size_t count)
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{
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struct page **pages;
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struct sg_table sgt;
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const void *p;
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int nr_pages;
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int index;
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int rc;
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/*
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* This is just a fast path if the caller has already created a
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* contiguous kernel buffer and the driver doesn't require SG, non-SG
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* drivers will still work on the slow path.
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*/
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if (mgr->mops->write)
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return fpga_mgr_buf_load_mapped(mgr, info, buf, count);
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/*
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* Convert the linear kernel pointer into a sg_table of pages for use
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* by the driver.
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*/
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nr_pages = DIV_ROUND_UP((unsigned long)buf + count, PAGE_SIZE) -
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(unsigned long)buf / PAGE_SIZE;
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pages = kmalloc_array(nr_pages, sizeof(struct page *), GFP_KERNEL);
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if (!pages)
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return -ENOMEM;
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p = buf - offset_in_page(buf);
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for (index = 0; index < nr_pages; index++) {
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if (is_vmalloc_addr(p))
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pages[index] = vmalloc_to_page(p);
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else
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pages[index] = kmap_to_page((void *)p);
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if (!pages[index]) {
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kfree(pages);
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return -EFAULT;
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}
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p += PAGE_SIZE;
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}
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/*
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* The temporary pages list is used to code share the merging algorithm
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* in sg_alloc_table_from_pages
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*/
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rc = sg_alloc_table_from_pages(&sgt, pages, index, offset_in_page(buf),
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count, GFP_KERNEL);
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kfree(pages);
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if (rc)
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return rc;
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rc = fpga_mgr_buf_load_sg(mgr, info, &sgt);
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sg_free_table(&sgt);
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return rc;
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}
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EXPORT_SYMBOL_GPL(fpga_mgr_buf_load);
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/**
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* fpga_mgr_firmware_load - request firmware and load to fpga
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* @mgr: fpga manager
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* @info: fpga image specific information
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* @image_name: name of image file on the firmware search path
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*
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* Request an FPGA image using the firmware class, then write out to the FPGA.
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* Update the state before each step to provide info on what step failed if
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* there is a failure. This code assumes the caller got the mgr pointer
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* from of_fpga_mgr_get() or fpga_mgr_get() and checked that it is not an error
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* code.
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*
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* Return: 0 on success, negative error code otherwise.
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*/
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int fpga_mgr_firmware_load(struct fpga_manager *mgr,
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struct fpga_image_info *info,
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const char *image_name)
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{
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struct device *dev = &mgr->dev;
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const struct firmware *fw;
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int ret;
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dev_info(dev, "writing %s to %s\n", image_name, mgr->name);
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mgr->state = FPGA_MGR_STATE_FIRMWARE_REQ;
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ret = request_firmware(&fw, image_name, dev);
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if (ret) {
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mgr->state = FPGA_MGR_STATE_FIRMWARE_REQ_ERR;
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dev_err(dev, "Error requesting firmware %s\n", image_name);
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return ret;
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}
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ret = fpga_mgr_buf_load(mgr, info, fw->data, fw->size);
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release_firmware(fw);
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return ret;
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}
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EXPORT_SYMBOL_GPL(fpga_mgr_firmware_load);
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static const char * const state_str[] = {
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[FPGA_MGR_STATE_UNKNOWN] = "unknown",
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[FPGA_MGR_STATE_POWER_OFF] = "power off",
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[FPGA_MGR_STATE_POWER_UP] = "power up",
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[FPGA_MGR_STATE_RESET] = "reset",
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/* requesting FPGA image from firmware */
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[FPGA_MGR_STATE_FIRMWARE_REQ] = "firmware request",
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[FPGA_MGR_STATE_FIRMWARE_REQ_ERR] = "firmware request error",
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/* Preparing FPGA to receive image */
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[FPGA_MGR_STATE_WRITE_INIT] = "write init",
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[FPGA_MGR_STATE_WRITE_INIT_ERR] = "write init error",
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/* Writing image to FPGA */
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[FPGA_MGR_STATE_WRITE] = "write",
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[FPGA_MGR_STATE_WRITE_ERR] = "write error",
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/* Finishing configuration after image has been written */
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[FPGA_MGR_STATE_WRITE_COMPLETE] = "write complete",
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[FPGA_MGR_STATE_WRITE_COMPLETE_ERR] = "write complete error",
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/* FPGA reports to be in normal operating mode */
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[FPGA_MGR_STATE_OPERATING] = "operating",
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};
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static ssize_t name_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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struct fpga_manager *mgr = to_fpga_manager(dev);
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return sprintf(buf, "%s\n", mgr->name);
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}
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static ssize_t state_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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struct fpga_manager *mgr = to_fpga_manager(dev);
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return sprintf(buf, "%s\n", state_str[mgr->state]);
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}
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static DEVICE_ATTR_RO(name);
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static DEVICE_ATTR_RO(state);
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static struct attribute *fpga_mgr_attrs[] = {
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&dev_attr_name.attr,
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&dev_attr_state.attr,
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NULL,
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};
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ATTRIBUTE_GROUPS(fpga_mgr);
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struct fpga_manager *__fpga_mgr_get(struct device *dev)
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{
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struct fpga_manager *mgr;
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int ret = -ENODEV;
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mgr = to_fpga_manager(dev);
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if (!mgr)
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goto err_dev;
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/* Get exclusive use of fpga manager */
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if (!mutex_trylock(&mgr->ref_mutex)) {
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ret = -EBUSY;
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goto err_dev;
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}
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if (!try_module_get(dev->parent->driver->owner))
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goto err_ll_mod;
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return mgr;
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err_ll_mod:
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mutex_unlock(&mgr->ref_mutex);
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err_dev:
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put_device(dev);
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return ERR_PTR(ret);
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}
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static int fpga_mgr_dev_match(struct device *dev, const void *data)
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{
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return dev->parent == data;
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}
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/**
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* fpga_mgr_get - get an exclusive reference to a fpga mgr
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* @dev: parent device that fpga mgr was registered with
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*
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* Given a device, get an exclusive reference to a fpga mgr.
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*
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* Return: fpga manager struct or IS_ERR() condition containing error code.
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*/
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struct fpga_manager *fpga_mgr_get(struct device *dev)
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{
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struct device *mgr_dev = class_find_device(fpga_mgr_class, NULL, dev,
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fpga_mgr_dev_match);
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if (!mgr_dev)
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return ERR_PTR(-ENODEV);
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return __fpga_mgr_get(mgr_dev);
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}
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EXPORT_SYMBOL_GPL(fpga_mgr_get);
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static int fpga_mgr_of_node_match(struct device *dev, const void *data)
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{
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return dev->of_node == data;
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}
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/**
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* of_fpga_mgr_get - get an exclusive reference to a fpga mgr
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* @node: device node
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*
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* Given a device node, get an exclusive reference to a fpga mgr.
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*
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* Return: fpga manager struct or IS_ERR() condition containing error code.
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*/
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struct fpga_manager *of_fpga_mgr_get(struct device_node *node)
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{
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struct device *dev;
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dev = class_find_device(fpga_mgr_class, NULL, node,
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fpga_mgr_of_node_match);
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if (!dev)
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return ERR_PTR(-ENODEV);
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return __fpga_mgr_get(dev);
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}
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EXPORT_SYMBOL_GPL(of_fpga_mgr_get);
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/**
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* fpga_mgr_put - release a reference to a fpga manager
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* @mgr: fpga manager structure
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*/
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void fpga_mgr_put(struct fpga_manager *mgr)
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{
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module_put(mgr->dev.parent->driver->owner);
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mutex_unlock(&mgr->ref_mutex);
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put_device(&mgr->dev);
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}
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EXPORT_SYMBOL_GPL(fpga_mgr_put);
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/**
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* fpga_mgr_register - register a low level fpga manager driver
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* @dev: fpga manager device from pdev
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* @name: fpga manager name
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* @mops: pointer to structure of fpga manager ops
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* @priv: fpga manager private data
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*
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* Return: 0 on success, negative error code otherwise.
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*/
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int fpga_mgr_register(struct device *dev, const char *name,
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const struct fpga_manager_ops *mops,
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void *priv)
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{
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struct fpga_manager *mgr;
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int id, ret;
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if (!mops || !mops->write_complete || !mops->state ||
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!mops->write_init || (!mops->write && !mops->write_sg) ||
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(mops->write && mops->write_sg)) {
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dev_err(dev, "Attempt to register without fpga_manager_ops\n");
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return -EINVAL;
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}
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if (!name || !strlen(name)) {
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dev_err(dev, "Attempt to register with no name!\n");
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return -EINVAL;
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}
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mgr = kzalloc(sizeof(*mgr), GFP_KERNEL);
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if (!mgr)
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return -ENOMEM;
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id = ida_simple_get(&fpga_mgr_ida, 0, 0, GFP_KERNEL);
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if (id < 0) {
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ret = id;
|
|
goto error_kfree;
|
|
}
|
|
|
|
mutex_init(&mgr->ref_mutex);
|
|
|
|
mgr->name = name;
|
|
mgr->mops = mops;
|
|
mgr->priv = priv;
|
|
|
|
/*
|
|
* Initialize framework state by requesting low level driver read state
|
|
* from device. FPGA may be in reset mode or may have been programmed
|
|
* by bootloader or EEPROM.
|
|
*/
|
|
mgr->state = mgr->mops->state(mgr);
|
|
|
|
device_initialize(&mgr->dev);
|
|
mgr->dev.class = fpga_mgr_class;
|
|
mgr->dev.parent = dev;
|
|
mgr->dev.of_node = dev->of_node;
|
|
mgr->dev.id = id;
|
|
dev_set_drvdata(dev, mgr);
|
|
|
|
ret = dev_set_name(&mgr->dev, "fpga%d", id);
|
|
if (ret)
|
|
goto error_device;
|
|
|
|
ret = device_add(&mgr->dev);
|
|
if (ret)
|
|
goto error_device;
|
|
|
|
dev_info(&mgr->dev, "%s registered\n", mgr->name);
|
|
|
|
return 0;
|
|
|
|
error_device:
|
|
ida_simple_remove(&fpga_mgr_ida, id);
|
|
error_kfree:
|
|
kfree(mgr);
|
|
|
|
return ret;
|
|
}
|
|
EXPORT_SYMBOL_GPL(fpga_mgr_register);
|
|
|
|
/**
|
|
* fpga_mgr_unregister - unregister a low level fpga manager driver
|
|
* @dev: fpga manager device from pdev
|
|
*/
|
|
void fpga_mgr_unregister(struct device *dev)
|
|
{
|
|
struct fpga_manager *mgr = dev_get_drvdata(dev);
|
|
|
|
dev_info(&mgr->dev, "%s %s\n", __func__, mgr->name);
|
|
|
|
/*
|
|
* If the low level driver provides a method for putting fpga into
|
|
* a desired state upon unregister, do it.
|
|
*/
|
|
if (mgr->mops->fpga_remove)
|
|
mgr->mops->fpga_remove(mgr);
|
|
|
|
device_unregister(&mgr->dev);
|
|
}
|
|
EXPORT_SYMBOL_GPL(fpga_mgr_unregister);
|
|
|
|
static void fpga_mgr_dev_release(struct device *dev)
|
|
{
|
|
struct fpga_manager *mgr = to_fpga_manager(dev);
|
|
|
|
ida_simple_remove(&fpga_mgr_ida, mgr->dev.id);
|
|
kfree(mgr);
|
|
}
|
|
|
|
static int __init fpga_mgr_class_init(void)
|
|
{
|
|
pr_info("FPGA manager framework\n");
|
|
|
|
fpga_mgr_class = class_create(THIS_MODULE, "fpga_manager");
|
|
if (IS_ERR(fpga_mgr_class))
|
|
return PTR_ERR(fpga_mgr_class);
|
|
|
|
fpga_mgr_class->dev_groups = fpga_mgr_groups;
|
|
fpga_mgr_class->dev_release = fpga_mgr_dev_release;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void __exit fpga_mgr_class_exit(void)
|
|
{
|
|
class_destroy(fpga_mgr_class);
|
|
ida_destroy(&fpga_mgr_ida);
|
|
}
|
|
|
|
MODULE_AUTHOR("Alan Tull <atull@opensource.altera.com>");
|
|
MODULE_DESCRIPTION("FPGA manager framework");
|
|
MODULE_LICENSE("GPL v2");
|
|
|
|
subsys_initcall(fpga_mgr_class_init);
|
|
module_exit(fpga_mgr_class_exit);
|